CDM Dependence on Device Capacitance
This blog will focus on what happens during the CDM pulse itself, and will show how the pulse properties change as a function of DUT to Field Plate capacitance.
Vendor:
Certus Semiconductor
Category:
GPIO
1.8V/3.3V GPIO Compliant with Multiple Standards in TSMC 16nm
High-Voltage Single-Ended / Differential I/O Macro in TSMC 16FFC This library is a high-voltage GPIO I/O Macro in TSMC 16nm.
Overview
High-Voltage Single-Ended / Differential I/O Macro in TSMC 16FFC
This library is a high-voltage GPIO I/O Macro in TSMC 16nm. The high-voltage GPIO is a flip-chip compatible 1.8V to 3.3V GPIO design, compliant with multiple I/O standards. It comes as a macro cell with a pair of I/Os in each cell, allowing differential I/O interface capabilities as well.
Operating Conditions
| Parameter | Value |
| Devices | 1.8V Thick and 0.8V Thin Oxides |
| BEOL | 11 Metals |
| VDDIO | 1.8V, 2.5V, or 3.3V Dynamic |
| VDD | 0.8V |
| Tj | -40C to 125C |
| ESD | +/- 2kV HBM, +/- 500V CDM |
Cell Names
| Cell Size | Metal Stack |
| RS_HVIO_DIF_NS | Pair of Digital GPIO, 70x75um |
| RS_HVIO_DIF_EW | Pair of Digital GPIO, 70x75um |
Single-Ended Standards
- LVCMOS: 8mA
- LVCMOS: 16mA
- SSTL Class 1
- SSTL Class 2
- PCI66
- PCIX133
Differential Standards
- LVDS
Key features
- Selectable I/O Standard Modes
- Selectable Single-Ended or Differential Operation
- Output enable/disable
- Selectable Pull-up and Pull-down resistors
- Selectable Slew Rates
Block Diagram
RS16_2 block diagram
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| TSMC | 16nm | 16nm 160 nm | — |
Specifications
Identity
Part Number
RS16_2
Vendor
Certus Semiconductor
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
United States
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Frequently asked questions about GPIO Pad Library IP cores
What is 1.8V/3.3V GPIO Compliant with Multiple Standards in TSMC 16nm?
1.8V/3.3V GPIO Compliant with Multiple Standards in TSMC 16nm is a GPIO IP core from Certus Semiconductor listed on Semi IP Hub. It is listed with support for tsmc.
How should engineers evaluate this GPIO?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this GPIO IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.