CDM Dependence on Device Capacitance
This blog will focus on what happens during the CDM pulse itself, and will show how the pulse properties change as a function of DUT to Field Plate capacitance.
Vendor:
Certus Semiconductor
Category:
GPIO
0.9V/2.5V I/O Library in TSMC 55nm
A 0.9V/2.5V In-Line I/O Library in TSMC 55LP.
Overview
A 0.9V/2.5V In-Line I/O Library in TSMC 55LP.
This SoundWire Digital I/O Library in TSMC 55nm LP is a silicon-proven interface solution for high-performance au- dio applications. Designed for 0.9V/2.5V operation, the Data, Clock, and Select I/Os, ensuring seamless integration with SoundWire-based systems. Engineered for reliability, the I/O cells meet 2kV HBM, 500V CDM, and 8kV system-level ESD protection (150pF, 330 Ohm direct contact to housing), with 18kV air discharge capability, offering exceptional robustness against electrostatic and environmental stress. This library is ideal for low-power, high-fidelity audio-designs, this I/O library deliver high signal integrity and compliance with industry standards.
Operating Conditions
| Feature | Value |
| Core Device | 0.9V Standard |
| I/O Device | 2.5V Standard |
| BEOL | 1P9M |
| PAD | CUP, 60um pitch |
| Cell Height | 80um |
| VDD Core | 0.9V +/- 10% |
| VDDIO | 1.2V to 1.8V |
| Tj | -40C to 125C |
| ESD | 2kV HBM, 500V CDM, Latch-up Immune |
Cell Names
| Cell Name | Cell Type |
| TE_DVSS | GND/Substrate |
| TE_AVSS | GND/Substrate |
| TE_AVDD | Power Pad |
| TE_DVDD | Power Pad |
| TE_ANA | Analog I/O |
| TE_DATA | Digital I/O |
| TE_CLK | Digital I/O |
| TE_SELECT | Digital I/O |
Key features
- SELECT I/O Features
- 6.5V Tolerant OTP input
- Schmitt Trigger Input
- 10Mhz digital output mode
- 1.8Mohm input pulldown
- DATA I/O Features
- Power down mode
- Output enable/disable
- Analog test point
- Level Shifting Input
- Trimmable delay circuit
- CLOCK I/O Features
- Power down mode with clock monitoring
- Schmitt Trigger
- Level Shifting Input
- Trimmable delay circuit
- Internal 3Mohm pull-down resistor
Block Diagram
TE55 block diagram
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| TSMC | 55nm | LP | — |
Specifications
Identity
Part Number
TE55
Vendor
Certus Semiconductor
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
United States
Learn more about GPIO IP core
A Low-Leakage Digital Foundation for SkyWater 90nm SoCs: Introducing Certus’ Standard Cell Library
As semiconductor designs continue to diversify, many successful products are not chasing the most advanced process nodes. Instead, they prioritize power efficiency, reliability, and long-term availability.
Field Induced CDM Explained
Integrated circuits are commonly tested for ESD robustness with 2 tests, Human Body Model (HBM) and Charged Device Model (CDM). Most engineers quickly grasp the procedure for HBM, but the CDM test is often poorly understood. This is unfortunate, because a large fraction of the ESD failures experienced in modern board assembly operations are CDM type failures. This article will describe the events which occur during a CDM test conducted using the widely accepted field induced CDM (FCDM) test.
One Platform, Five Libraries: Certus Semiconductor’s I/O IP Portfolio for Every Application on TSMC 22nm ULL/ULP Technologies
Certus Semiconductor’s I/O libraries for TSMC’s 22nm ultra-low leakage (22ULL) and 22nm ultra-low power (22ULP) technologies offer robust, high-performance solutions tailored to a wide range of SoC designs — from ultra-low power IoT nodes to demanding consumer and automotive systems. Whether you need low leakage, high drive strength, or analog compatibility, our production-proven IP covers it all.
Certus Semiconductor Joins TSMC IP Alliance Program to Enhance Custom I/O and ESD Solutions
As a member of the TSMC IP Alliance, Certus delivers production-proven IP that ensures seamless integration with TSMC process nodes, ranging from 180nm to 12nm.
Unlocking High-Speed Connectivity with Certus Semiconductor’s LVDS Transceiver on GlobalFoundries 12LP/LP+
In today’s data-driven world, high-speed, low-power communication is essential. Certus Semiconductor’s LVDS Transceiver delivers exactly that—optimized for GlobalFoundries’ 12nm CMOS process, it provides reliable, high-performance Low-Voltage Differential Signaling (LVDS) for next-generation designs.
Frequently asked questions about GPIO Pad Library IP cores
What is 0.9V/2.5V I/O Library in TSMC 55nm?
0.9V/2.5V I/O Library in TSMC 55nm is a GPIO IP core from Certus Semiconductor listed on Semi IP Hub. It is listed with support for tsmc.
How should engineers evaluate this GPIO?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this GPIO IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.