Near-Memory AI Acceleration Platform Delivering Maximum Performance per Watt
- Edge AI Accelerator
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Near-Memory AI Acceleration Platform Delivering Maximum Performance per Watt
The mesh interconnect is a scalable, high-performance communication fabric designed to connect a large number of master and slave devices in complex SoC architectures.
Compliant with the JPEG XL (ISO/IEC JTC 1/SC29/WG1 18181) standard.
I2C Master/Slave Controller Core
Compatible with Philips I2C Specification version 2.1.
Compliant and interoperable with standards defined by UNH_IOL.
SWI3S (SoundWire I3S Interface) Peripheral Controller Core IP
Implements & supports MIPI SoundWire-I3S Specification
Low Power 32kHz Pierce Oscillator
Ultra-low power consumption: 489 nA max average current
Graphics, compute and AI all on one processor, with one software stack
FlexGen Multi-Die Smart Network-on-Chip (NoC) IP
AI-enhanced automation for smarter multi-die SoC and chiplet designs.
Ncore Multi-Die Interconnect IP
High-bandwidth, low-latency network-on-chip (NoC) interconnect for rapid modular innovation.
CryptoManager Root of Trust for Use with the Caliptra Specification
Root of Trust and Security Orchestration for Caliptra-based SoCs
Meets the requirements of 10,000-scale XPU clusters and high performance storage
High Performance, Small Area, Low Power | Flexible Controller Configuration Solution
Supports full protocol coverage from USB 2.0 to USB 3.2 Certified by USB-IF
This TSMC 3nm 1.8V GPIO IP provides configurable, overvoltage-tolerant I/O functionality for advanced-node designs. The IP macro is designed in TSMC 3nm.
This TSMC 2nm 1.8V GPIO IP provides configurable, overvoltage-tolerant I/O functionality for advanced-node designs. The IP macro is designed in TSMC 2nm.
Silicon Library (SLI) HDMI 2.0 RX IP solution, which consists of PHY analog IP and digital LINK IP, is compliant with HDMI 2.0b standard.
Silicon Library (SLI) HDMI 2.0 TX IP solution, which consists of analog PHY IP and digital LINK IP, is compliant with HDMI 2.0b standard.
Analog Switch with Gate Voltage Booster on TSMC 40nm
This Analog Switch IP contains 3 cells of Charge Pump, 500Ω Switch and 2kΩ Switch.
This OPAMP has rail-to-rail input and wide power supply voltage range on T40ULP ESF3.