AXI NoC Non-Coherent Mesh

The mesh interconnect is a scalable, high-performance communication fabric designed to connect a large number of master and slave devices in complex SoC architectures. Based on a distributed mesh topology, the interconnect enables efficient routing of transactions across the fabric while maintaining low and deterministic latency. It supports AXI compliant interfaces, allowing seamless integration of high-performance processing elements and low-speed peripheral subsystems within a unified interconnect framework.

To maximize throughput, the interconnect supports parallel processing of read and write channels and provides configurable transaction ordering to meet application-specific performance and dependency requirements. Multiple routing algorithms are supported, enabling designers to optimize traffic flow for latency, bandwidth, or congestion avoidance. The internal network data width is configurable, allowing flexible trade-offs between performance, power, and area.

System integration and reliability are addressed through rich configurability and control features. Configurable register mapping enables flexible address space organization aligned with system software requirements. Advanced interrupt management supports efficient system-level event handling, while per-channel watchdog timers provide detection of stalled or abnormal transactions. Independent software controlled reset for each master and slave interface allows localized fault isolation without impacting overall system operation.

The interconnect is designed to operate in complex clocking and power environments. Register slicing is supported for asynchronous interfaces to simplify clock-domain crossings and timing closure. Each master and slave interface can operate in an independent clock domain, and internal clock gating reduces dynamic power consumption during idle or low activity periods. With deterministic single-cycle transaction traversal latency, the mesh interconnect provides a robust, scalable, and high performance solution for modern multi-master SoC platforms.

Delivered as a synthesizable RTL IP optimized for power, performance, and area (PPA), the AXI NoC integrates seamlessly into AMBA-based infrastructures. By combining a high-speed mesh topology, multi protocol AMBA compliance, NoC-level scalability, and rich configurability, the AXI NoC provides a robust, production-ready interconnect solution for next-generation scalable SoC designs.

• Scalable crossbar interconnect architecture
• Cascaded NoC support for large master/slave counts
• AXIcompliant interfaces
• Configurable arbitration and transaction ordering
• Configurable register mapping
• Advanced interrupt management
• Per-channel watchdog timers
• Independent master and slave software reset
• Register slicing for asynchronous interfaces
• Internal clock gating support
• Parallel processing of write & read channel for each master
• Deterministic latency: 4-cycle request, 3-cycle response
• Configurable internal data width
• Independent master and slave clock domains

• Ip generator & config tool
• Verilog Testbench with Verilog Testcases
• CDC constraints file (.sdc)
• IP analysis reports
  • Linting report
  • Synthesis report
  • CDC report
  • Code Coverage Exception file
• Simulation script
• IP Block Guide
• IPG Guide
• Integration Guide