Vendor: Atria Logic, Inc. Category: NVMe Controller

NVMe Validation Test Suite

Compliant and interoperable with standards defined by UNH_IOL.

Verification IP View all specifications

Overview

Non Volatile Memory Express (NVMe) is an interface controller specification built for accessing Solid State Drives(SSD) over a PCIe channel. NVMe has enabled greater data I/O and throughput performance of Flash based SSD storage units. NVMe has gained more traction in recent days due to their high performance benefits over its counterpart.

Atria Logic NVMe (AL_NVMe) post silicon test validation suite offers an environment for system level validation of NVMe Controller. The test suite defined is compliant and interoperable with standards defined by UNH_IOL. Additionally, it also provides other test features for greater confidence on the design and performance. It supports Linux based environment with ease of portability across systems.

Architecture

The validation environment is developed from off the shelf hardware and software components. The Atria NVMe Validation suite has Intel Galileo Development board and Xilinx Zynq ARM based FPGA SoC. The development boards can be interchangeably used as a host and Endpoint.

Key features

  • Environment developed from off the shelf Hardware and Software Components.
  • Test Suite compliant and interoperable with UNH_IOL.
  • Software Components are easily portable to Linux, RTOS or bare-metal environments.
  • Environment replication is easy even at Customer's site.
  • Simulates the environment for verifying PCIe root complex, Endpoint as well as NVMe controller functionality.
  • Zynq SoC configurable hardware to add custom blocks with software configuration and control
    • Bus Analyzer
    • Performance statistics
    • Diagnostics
  • The Performance monitors in the Endpoint driver gives statistical information on the data movement.
  • QEMU based NVMe simulation environment.
  • This platform can be customized to use validate peripheral functionalities.
  • The test suite allows flexibility to use either x86/ARM platforms.
  • GUI based environment to initiate test cases and provide statistical performance data.

Block Diagram

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What’s Included?

  • tNVME + dNVMe framework.
  • Custom driver for performance verification.
  • NVMe endpoint virtual driver.
  • Java based Application for GUI interface.

Specifications

Identity

Part Number
AL_NVMe
Vendor
Atria Logic, Inc.
Type
Verification IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Learn more about NVMe Controller IP core

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High Bandwidth Memory (HBM) Model & Verification IP Implementation - Beginner's guide

With ever increasing need for very high operating frequency of graphics (GPU) or general purpose (CPU) processors, the limited memory bandwidth forms a bottleneck to extract maximum performance out of a system. To add to this, low power consumption, form factor of the memory devices also play significant roles in optimal and efficient solutions.

Design Considerations for High Bandwidth Memory Controller

High Bandwidth Memory (HBM) is a high-performance 3D-stacked DRAM. It is a technology which stacks up DRAM chips (memory die) vertically on a high speed logic layer which are connected by vertical interconnect technology called TSV (through silicon via) which reduces the connectivity impedance and thereby total power consumption.

Frequently asked questions about NVMe Controller IP cores

What is NVMe Validation Test Suite?

NVMe Validation Test Suite is a NVMe Controller IP core from Atria Logic, Inc. listed on Semi IP Hub.

How should engineers evaluate this NVMe Controller?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this NVMe Controller IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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