Vendor: Arteris Category: Network-On-Chip

Ncore Multi-Die Interconnect IP

High-bandwidth, low-latency network-on-chip (NoC) interconnect for rapid modular innovation.

ASIL B View all specifications

Overview

Solve multi-core design challenges with safety support

Ncore Multi-Die is a configurable cache‑coherent interconnect with optional last‑level caches that supports full CPU cache coherency and I/O coherency for high‑performance system designs.

Ncore Multi‑Die extends the Ncore coherent interconnect across multiple chiplets, enabling scalable, high‑performance architectures that overcome reticle limits and, yield challenges, and addresses the growing requirement for modular compute and silicon process specialization in AI, automotive, HPC, and data‑centric SoCs.

Create high-performance coherent SoCs

Scale Performance with Multi-Die Coherency

By extending Ncore coherency across up to four dies, designers can scale performance linearly through homogeneous replication or mix heterogeneous compute resources using the best process technology for each domain. Coherency remains transparent to software, preserving standard programming models.

Increase Bandwidth and Reduce Latency

With over 64 GB/s usable data bandwidth per link, and 256 GB/s per die, Ncore Multi‑Die provides the bandwidth needed for AI/ML and HPC workloads. Interleaving and link aggregation boost point‑to-point throughput, while message forwarding in the GIU minimizes latency.

Tune Systems for Flexibility and Design Requirements

Support for mesh and fully connected homogeneous or heterogeneous chiplet interconnect topologies allows designers to tailor the system for performance, cost, or physical layout constraints. Logical‑to‑physical remapping enables die rotation or mirroring while maintaining correct routing, easing interposer design.

Key features

  • Cache coherency extended across 2 to 4 chiplets
  • Link Ncore Multi-Die instances together into a single coherency domain
  • Fully coherent die-to-die bridging via the gateway interface unit (GIU)
  • Homogeneous and heterogeneous chiplet support
  • Up to 16 coherent initiator ports per die
  • Last-level caches for memory interfaces and proxy caches for integrating I/O initiators
  • Automated mesh topology generation and physical tiling
  • PCIe acceleration for high-performance I/O
  • AMBA CXS.B interface to UCIe controllers and PHYs
  • Up to 4 UCIe 1.1 Advanced (4x 64 lanes@ 16 GT/s) die‑to‑die links per chiplet
  • Up to 128 GB/s peak bandwidth per link (usable data bandwidth >64 GB/s / link)
  • Mesh or fully connected (point-to-point) chiplet topologies
  • Link remapping for die rotation and reflection, easing interposer routing
  • Global NUMA address map with local‑optimized memory access
  • Cross‑die DVM messaging for Arm System MMU control
  • Pre‑integrated and verified with select UCIe controllers for faster time‑ to‑silicon
  • Configuration of each unique chiplet and top-level chiplet connectivity within an intuitive graphical tooling environment
  • Optional Resilience/Safety package for ISO 26262

Benefits

  • Higher frequencies, lower latencies: Use of multiple configurable snoop filters to accommodate different cache organization.
  • Lower power consumption: Fewer off-chip main memory accesses result in lower power consumption.
  • Smaller die area: Fewer wires use the optimal NoC transport layer.
  • Easy configuration: Ncore adapts to each coherent agent’s behavior and characteristics.
  • Faster time to market: Tiling accelerates physical design, implementation, and timing closure.
  • Flexible topologies: Choose from crossbar, mesh, and ad-hoc topologies.
  • Safety: Automated FMEDA safety documentation and ISO26262 ASIL B to D certified.
  • Automated verification: Save hundreds of hours of work compared to manual verification generation.
  • Shorter schedules: Fewer iteration loops speed development time.

Specifications

Identity

Part Number
Ncore Multi-Die Interconnect IP
Vendor
Arteris
Type
Silicon IP

Safety & Qualification

Functional Safety Level
ASIL B

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Arteris
HQ: United States

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Frequently asked questions about NoC IP cores

What is Ncore Multi-Die Interconnect IP?

Ncore Multi-Die Interconnect IP is a Network-On-Chip IP core from Arteris listed on Semi IP Hub.

How should engineers evaluate this Network-On-Chip?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Network-On-Chip IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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