FlexGen Multi-Die Smart Network-on-Chip (NoC) IP

Intelligent NoC automation for next-gen SoC design

Arteris FlexGen® Multi-Die adds die-to-die controller IP, for chiplet-to-chiplet interconnect to Arteris FlexGen smart NoC IP, leveraging its cutting-edge AI heuristics and machine learning, and automating NoC topology generation for monolithic and multi-die designs alike. This achieves up to 10 times faster design iterations than traditional manual NoC design methods.

• Optimize wire length.
• Reduce latency.
• Improve power efficiency.
• Efficiently connect FlexGen NoCs from chiplet to chiplet.
• Minimize manual intervention.

Designed for high performance compute (HPC) and AI accelerator applications for data centers, automotive, consumer, and industrial electronics applications, FlexGen Multi-Die shortens design cycles, enabling faster time-to-market and multiple design explorations for the most complex systems.

Advantages

The smart and efficient way to build SoCs 

10x productivity boost

Smart NoC generation is 10x faster than traditional NoC flows, shortening SoC or chiplet iterations from weeks to days for design efficiency.

Expert-level results

Minimal effort for top-quality results and three times improvement in engineering efficiency across all NoCs. Algorithms minimize routing congestion, improving silicon area during physical design, with proven links to physical synthesis, place, and route to support tape-out success.

Wire length reduction-driven performance

Smart AI heuristics using machine-learning technology deliver an optimized topology with an average wire length reduction of up to 30%, reducing overall latency by up to 10%, and delivering power improvements across the design.

Chiplet ready, multi-die interconnect

The FlexGen die-to-die controller packages the NoC transport protocol using a highly configurable FLIT format to maximize PHY flexibility and minimize bandwidth overhead, latency, area, and power, and can be used with a wide variety of third party industry standard PHYs, including UCIe and BoW.

• Smart NoC automation
• Topology generation with minimum wire length
• Scripting-driven regular topology creation
• Incremental design capability
• Die-to-die controller with highly configurable FLIT format, supporting up to eight independent receive and transmit virtual channels with credited links.
• Auto-timing closure assist
• … plus all the key features of FlexGen 1 and FlexNoC 5

• Expert-level output quality: Generated smart NoC architecture and physical constraints.
• Significant reductions in wire length: Minimize die area, power consumption, and latency.
• 10x productivity improvement: Reduce setup and configuration time from days to hours or minutes by automating repetitive, time-intensive tasks.
• Higher frequencies, lower latencies: Use built-in NoC performance analysis exploration tools.
• Speedy timing closure: Early physical awareness results in faster convergence without re-designs.
• Automated verification: Save hundreds of hours of work versus manual verification test benches.
• Increased profit: Reduce time to market with FlexGen design efficiency savings.
• PHY agnostic D2D controller: Highly configurable FLIT format supports a wide variety of third party industry standard PHY IP, e.g. UCI, BoW, etc.