SmartDV’s UCIe 3.x Controller IP is a next-generation Universal Chiplet Interconnect Express solution engineered for the most dem…
- Controller
SmartDV’s UCIe 3.x Controller IP is a next-generation Universal Chiplet Interconnect Express solution engineered for the most dem…
Industry , AXI5-Stream Solution for UCIe D2D Stacks The AXI-S Protocol Layer for UCIe is a protocol adapter layer between a Strea…
Accelerated confidence in simulation-based verification of RTL designs with Universal Chiplet Interconnect Express (UCIe) interfa…
BlueLynx PHY IP is one side of a die-to-die parallel interface delivered as a single GDS Hard IP and a single RTL Soft IP.
Verification IP for Universal Chiplet Interconnect Express (UCIe) up to 3.0
Specifications: UCIe v1.0, v1.1, v2.0, v3.0 Interfaces: FDI/RDI/PHY link DUT Types/Topology D2D Adapter, Phy, Protocol, Full Stac…
Hardware link (de)compression IP for die-to-die, chip-to-chip, and DRAM interfaces
Expands effective bandwidth across links and memory interfaces with deterministic, data-independent latency, fully pipelined to sustain line rate
UCIe Controller (CHI Protocol + Adapter)
The UCIe Controller consists of Universal Chiplet Interconnect Express (UCIe) Die-to-Die (D2D) Adapter and Protocol Layers.
UCIe Controller (AXI Protocol + Adapter)
The UCIe Controller consists of Universal Chiplet Interconnect Express (UCIe) Die-to-Die (D2D) Adapter and Protocol Layers.
TSMC CLN5FF GUCIe LP Die-to-Die PHY
IGAD2DY11A is an LP (Low Power) Die-to-Die (D2D) PHY for SoIC-X Face-to-Face package.
The UCIe Chiplet IP offers a cutting-edge solution for seamless, low-latency data transfer between dies and chips, enabling heter…
The UCIe IP solution includes D2D Adapter layer which supports streaming/PCIe/CXL/Raw flitformats, supports both standard and mai…
Best-in-Class UCIe Verification IP for your IP, SoC, and System-Level Design Testing The Cadence Verification IP (VIP) for Univer…
Our mass production-proven IPTD2D-A D2D Interconnect IP Solutions offer industry- power efficiency, performance, and low latency,…
The NuLink technology delivers low-power and high-performance D2D IP core products, which support multiple industry standards and…
Streamline Ventana technology integration into high-performance systems, fully leveraging third-party IP, while applying RISC-V s…
The UCIe PHY IP enables high-bandwidth, low-latency die-to-die communication across chiplets, fully compliant with the Universal …
The MIPI I3C Controller IP is a optimized and technology agnostic implementation of the MIPI I3C v.1.1.1 standard targeting both …
The MIPI I3C Controller IP is a optimized and technology agnostic implementation of the MIPI I3C v.1.1.1 standard targeting both …
The MIPI I3C Controller IP is a optimized and technology agnostic implementation of the MIPI I3C v.1.1.1 standard targeting both …
MIPI I3C Secondary Controller IP core
The MIPI I3C Controller IP is a optimized and technology agnostic implementation of the MIPI I3C v.1.1.1 standard targeting both …