AXI-S Protocol Layer for UCIe

Industry Leading, AXI5-Stream Solution for UCIe D2D Stacks

The AXI-S Protocol Layer for UCIe is a protocol adapter layer between a Streaming AXI Bus and the FDI interface of the UCIe D2D Adapter. It allows for efficient communication across chiplets using the light weight AXI Streaming Protocol. The IP includes both the TX and RX direction with configurable data bus width and the expected ready valid handshaking with wakeup capability, strb, keep, last indications for data flagging,  id, dest for steam identification and routing and the user sideband information.

The IP Core is silicon and PHY agnostic implementation of AXI5 Stream Protocol Layer for UCIe following the v2.0 standard, targeting ASIC applications. The IP core is thoroughly tested in System Verilog random regression environment. The IP comes with a parameter based flexible data bus width and has gone through extensive testing. The IP core is silicon proven, heavily tested in UVM regression environment and has been interoperability tested and integrated with a leading UCIe PHY provider.

The AXI-S Protocol Layer interfaces to the UCIe Die to Die Adapter IP with the Flit-Aware Die to Die Interface (FDI). The IP is customizable in its data width and contains all the necessary features for compliant AXI-S transfers across UCIe.

• Configurable Data width
• AXI4 Stream and AXI5 Stream Compliant
• All handshaking features including wakeup
• strb and keep for data flagging
• id and destination for stream identification and routing
• User sideband information supported
• Silicon Agnostic

• Test Environment: UCIe AXI-S Protocol Layer is Tested in a UVM regression environment for full functional coverage
• Silicon Agnostic: Designed in Verilog and targeting both ASICs and FPGAs
• UCIe PHY Integration: PHY Integration support with additional hours or off the shelf UCIe D2D Adapter and UCIe PHY integration package for quick and efficient deployment
• Active Support: All support is actively provided by engineers directly

The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:

• Solid documentation, including User Manual, Release Note and Quick Start Guide.
• Simulation Environment, including Simple Testbed, Test case, Test Script.
• Timing Constraints in Synopsys SDC format.
• Access to support system and direct support from Chip Interfaces Engineers.
• Test Report , Synopsys SGDC Files and Synopsys Lint, CDC and Waivers available on request