Vendor: ZeroPoint Technologies AB Category: Data Compression

Hardware link (de)compression IP for die-to-die, chip-to-chip, and DRAM interfaces

Expands effective bandwidth across links and memory interfaces with deterministic, data-independent latency, fully pipelined to sustain line rate

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Overview

Hardware link (de)compression IP for streaming bandwidth expansion across die-to-die, chip-to-chip, and DRAM interfaces. Fully pipelined to sustain line rate, with deterministic, data-independent latency.

ZeroStream is a hardware compression and decompression IP block that expands effective memory bandwidth for AI accelerators. It compresses data in real time as it moves across a link or memory interface, so more useful data is delivered per cycle without changing the host software or retraining models.

Why it matters

Compression ratio translates directly into throughput on bandwidth-bound workloads. For LLM decode, which is memory bound, more effective bandwidth means more tokens per second from the same silicon and the same memory.

Software library included

The IP solution ships with a software library that adapts the encoding to different LLM models and data types for higher compression efficiency and optimal bandwidth. The library is transparent to the user and the system.

Key specifications

Headline characteristics below. Area, gate count, and cycle-level latency figures are configuration dependent.

Target data Any data. Examples: weights, activations, KV cache, databases, data center class workloads.
Use cases Die-to-die, chip-to-chip, and DRAM bandwidth improvement.
Max clock frequency Up to 2 GHz (Samsung 4nm).
Bandwidth at 2 GHz 512-bit interface: 128 GB/s per direction (compress + decompress). 256-bit interface: 64 GB/s per direction.
Compression ratio Up to 1.5x on LLM weights; an average of 2x on activations and KV cache.
Bandwidth improvement 20–35% across data types, up to 50%.
Data interface AXIStream, 256-bit or 512-bit.
Latency Deterministic and data-independent. Approximately 20 cycles at 2 GHz.
Metadata Approximately 0.05% overhead to track the compression state of each superblock. Managed by the integrator or by the IP. No metadata management needed for C2C / D2D links.

Key features

  • Hardware compress and decompress
  • Deterministic, data-independent latency
  • Line-rate, fully pipelined throughput
  • Transparent software encoding library
  • No model retraining required

What’s Included?

  • Synthesizable RTL for compressor and decompressor.
  • Verification and test framework.
  • Transparent software encoding library.
  • Integration support and onsite consulting.

Specifications

Identity

Part Number
ZeroStream
Vendor
ZeroPoint Technologies AB
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact ZeroPoint Technologies AB

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Frequently asked questions about Data Compression IP

What is Hardware link (de)compression IP for die-to-die, chip-to-chip, and DRAM interfaces?

Hardware link (de)compression IP for die-to-die, chip-to-chip, and DRAM interfaces is a Data Compression IP core from ZeroPoint Technologies AB listed on Semi IP Hub.

How should engineers evaluate this Data Compression?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Data Compression IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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