Vendor: InPsy Category: Custom

IPTD2D-A PHY and Controller

Our mass production-proven IPTD2D-A D2D Interconnect IP Solutions offer industry- power efficiency, performance, and low latency,…

Overview

Our mass production-proven IPTD2D-A D2D Interconnect IP Solutions offer industry-leading power efficiency, performance, and low latency, tailored for the next generation of high-performance computing, AI, and data center applications. With asynchronous “side-band” signals, the IPTD2D PHY can work at any frequency ranging from 2Gbps to 16Gbps, achieving the best balance between total bandwidth and power consumption.

Key features

  • Supports CoWoSTM, INFOTM and EMIBTM package technologies
  • Supports any speed ranging from 2Gbps to 16Gbps, achieving the best balance between total bandwidth and power consumption
  • Available process nodes
    • TSMC N5 (Mass production proven)
    • TSMC N4P (Silicon proven)
    • TSMC N3E/N3P (Silicon proven)
  • 8-channel PHY with 64Tx/64Rx lanes per channel
  • Industry leading power consumption @0.238pj/bit (TSMC N3P process, PRBS31 pattern)
  • Extreme low End-to-end Latency
  • Industry leading Beach-front bandwidth
  • Patented voltage and Temperature Adaptive receiver to compensate voltage and temperature changes during transmission, result in zero or extreme low BER (Bit-Error-Rate)
  • Real-time per lane data-eye monitor to monitor the health of each lane real time
  • UCIe Controller supports all UCIe defined interfaces, AXI and CXS

Specifications

Identity

Part Number
IPTD2D-A PHY and Controller
Vendor
InPsy
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: Taiwan (R.O.C.)

Learn more about Custom IP core

Enabling RISC-V Vector Code Generation in MLIR through Custom xDSL Lowerings

The growing adoption of RISC-V in high-performance and scientific computing has increased the need for performance-portable code targeting the RISC-V Vector (RVV) extension. However, current compiler infrastructures provide limited end-to-end support for generating optimized RVV code from high-level representations to low-level implementations. In particular, existing MLIR distributions lack practical lowering paths that map high-level abstractions to RVV intrinsics, limiting their applicability for production-ready RISC-V kernels. This paper presents a compilation approach that combines MLIR with xDSL to bridge the missing lowering stages required for RVV code generation.

RISC-V basics: The truth about custom extensions

The era of universal processor architectures is giving way to workload-specific designs optimized for performance, power, and scalability. As data-centric applications in artificial intelligence (AI), edge computing, automotive, and industrial markets continue to expand, they are driving a fundamental shift in processor design.

Frequently asked questions about Custom Die-to-Die IP cores

What is IPTD2D-A PHY and Controller?

IPTD2D-A PHY and Controller is a Custom IP core from InPsy listed on Semi IP Hub.

How should engineers evaluate this Custom?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Custom IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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