Vendor: Synopsys, Inc. Category: UCIe

Verification IP for Universal Chiplet Interconnect Express (UCIe) up to 3.0

Specifications: UCIe v1.0, v1.1, v2.0, v3.0 Interfaces: FDI/RDI/PHY link DUT Types/Topology D2D Adapter, Phy, Protocol, Full Stac…

Verification IP View all specifications

Overview

Specifications: UCIe v1.0, v1.1, v2.0, v3.0

Interfaces: FDI/RDI/PHY link

DUT Types/Topology

  • D2D Adapter, Phy, Protocol, Full Stack

Key VIP Features

  • CXL over UCIe, PCIe over UCIe, Streaming
  • Modes of operation: Active, Passive
  • API based transaction flow for ease of use
  • Specification-linked protocol checks and functional coverage
  • Exceptions, callbacks, error injection and analysis ports for Scoreboard
  • RDI Shim layer at D2D adapter for early test development
  • Configurable interpacket delays for mainband and sideband packets

Debug and Analysis

  • Debug Ports: ASCII string for LTSM states, Scramble/unscramble data, LFSR Rx/Tx data, Rx/Tx pattern detected
  • Multiple log options: UVM reporter, Transaction log for Sideband & Mainband

Available on SoC Verification Kit (SVK) for interoperability and subsystem/SoC level verification using Synopsys IP 

Key Protocol Features

  • Support for all Flit formats and Data Rates
  • Support for mainband, sideband, and DLLP data width
  • Standard and Advanced Package
  • Multi module support: x2 and x4
  • Clocking modes: Strobe, Continuous, Half rate and Quarter rate
  • Parity feature, CRC, Retry
  • Enhanced Multi-Protocol support
  • Power Management Link States, Cross combination of state request
  • Sideband MTP Support
  • Compliance support (Flit Injection & retry)
  • Repair feature support
  • Link width degrade, Speed degrade
  • Suports UCIe-S, SO, SPMO
  • Scrambling/Descrambling, Lane Reversal, Retrain and Error recovery

Test Suites / Groups Features

  • Test Groups based on the DUT Types: Full stack, D2D Adapter, Phy Control and status registers to enable software to test various combination of flows
  • Hooks for DUT integration in Test Bench

Block Diagram

Specifications

Identity

Part Number
Verification IP for Universal Chiplet Interconnect Express (UCIe) up to 3.0
Vendor
Synopsys, Inc.
Type
Verification IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

Learn more about Synopsys' UCIe IP core

40G UCIe IP Advantages for AI Applications

For AI workloads to be processed reliably at a fast rate, the die-to-die interface in multi-die designs must be robust, low latency, and most importantly high bandwidth. This article outlines the need for 40G UCIe IP in AI data center chips leveraging multi-die designs.

40G UCIe IP Advantages for AI Applications

For AI workloads to be processed reliably at a fast rate, the die-to-die interface in multi-die designs must be robust, low latency, and most importantly high bandwidth. This article outlines the need for 40G UCIe IP in AI data center chips leveraging multi-die designs.

Frequently asked questions about UCIe IP cores

What is Verification IP for Universal Chiplet Interconnect Express (UCIe) up to 3.0?

Verification IP for Universal Chiplet Interconnect Express (UCIe) up to 3.0 is a UCIe IP core from Synopsys, Inc. listed on Semi IP Hub.

How should engineers evaluate this UCIe?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this UCIe IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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