Synopsys Advances Die‑to‑Die Connectivity with 64G UCIe IP Tape‑Out
Discover Synopsys 64G UCIe IP for energy-efficient, high-bandwidth die-to-die connectivity in advanced multi-die AI and HPC designs.
Vendor:
Innosilicon Technology Ltd
Category:
UCIe
UCIe Chiplet PHY & Controller
The UCIe Chiplet IP offers a cutting-edge solution for seamless, low-latency data transfer between dies and chips, enabling heter…
Overview
The UCIe Chiplet IP offers a cutting-edge solution for seamless, low-latency data transfer between dies and chips, enabling heterogeneous integration for performance and efficiency gains. It supports die-to-die (D2D), chip-to-chip (C2C), interposer and PCB connectivity, ideal for data centers, 5G, HPC, and AI. The IP family includes UCIe-S (24Gbps/pin, 100um~150um pitch) for MCM/short PCB, and UCIe-A (32Gbps/pin, 25um~55um pitch) for silicon interposers. Both support scalable bandwidth (UCIe-A: 2048Gbps; UCIe-S: 384Gbps) with scalability for 1/2/4/8 modules and are compatible with UCIe standard and advanced package version.
Key features
- Compliant with the UCIe specification (2.0 & 1.1)
- Flexible Structure, easy to customize (Pre-hardened PHY tuned to Customer Spec, PHY + Adapter Layer, PHY + Adapter Layer + Customized Protocol Layer)
- Supports the CXS/AXI using the streaming package (AXI Interface bandwidth up to 89%)
- Supports the CXL/PCIE interface
- Fault Tolerance: Supports the CRC + Retry + FEC
- Supports FEC Mechanism (Optional)
- Low Power: Tunable Driver/Receiver Strength & auto clock gate (Clock Gate Ratio > 95%)
- Complete DFX mechanism for Debug
- Supports the Performance Monitor (bandwidth/latency monitor and event monitor)
- Supports the Complete BIST & On Die Scope mechanism (Covers protocol layer to the link layer)
- Supports the MCM, INFO, and Interposer package plus PCB
- High Performance: up to 24Gbps on MCM, 20Gbps on PCB, 32Gbps on interposer
- Auto Tracking: Forward Clock, Support PVT auto tracking
- Low Latency: Link layer latency to under 3ns
- Full training for the PHY Layer
- High Density: Standard Pitch and Micro Bump
Block Diagram
UCIe Chiplet block diagram
Benefits
- Fully pre-assembled design, Drop-in hard macro to ease integration and speed time to market
- Zero risk with robust ESD architecture
- Extensive EDA tool support for various design and automation flow
- Optional CKE retention mode permits VDD and all non-essential I/Os to be powered down while retaining the external SDRAMs in self-refresh mode
- Comprehensive observation registers DFX and methods are available to facilitate customers in identifying issues during testing
What’s Included?
- Extensive documentation
- Models
- LIB
- LEF
- Place-and-route abstracts
- LVS netlist
- GDSII files
Specifications
Identity
Part Number
UCIe Chiplet
Vendor
Innosilicon Technology Ltd
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
Innosilicon Technology Ltd
HQ:
China
Innosilicon is a world-class one-stop shop of high-speed interface IP and design services with 18 years of history. Having empowered hundreds of well-known customers including Qualcomm, AMD, Microsoft, Amazon, with all major process nodes covered across the world's top 6 foundries (TSMC/Samsung/GF/UMC/Intel/SMIC) from 55nm to 3nm, Innosilicon boasts over 1300 employees and is fully devoted to extending its leadership in delivering advanced IP and ASIC services. Our team offers unique IP such as HBM3E/2E Combo, GDDR7/6X/6 Combo, LPDDR5X/5/4X/4 Combo, DDR5 DIMM support, UCle Chiplet, various High-speed SerDes and HDMI2.1/eDP1.4 Combo, all with standard PHY and controller combinations as well as custom design options. Our outstanding innovation capabilities have been proven in high-performance computing, high-bandwidth memory, automotive, multimedia low-power IoT and other fields. We drastically improve our customer satisfaction and reduce time to market by offering our unique domain specific design platforms and flexible win-win business models.
Learn more about UCIe IP core
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In keeping with a rapidly broadening portfolio of die-to-die connectivity solutions, Cadence has taped out its IP subsystem for 32GT/s UCIe solution on Samsung's 4nm (SF4X) process technology.
UCIe D2D Adapter Explained: Architecture, Flit Mapping, Reliability, and Protocol Multiplexing
Understand the role of the UCIe D2D Adapter in enabling reliable, scalable, multi-protocol die-to-die communication for chiplet architectures.
The Next-Generation UCIe IP Subsystem for Advanced Package Designs
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Cadence Silicon Success of UCIe IP on Samsung Foundry’s 5nm Automotive Process
Cadence has successfully demonstrated first-pass silicon success of its UCIe™ standard package IP on Samsung Foundry's 5nm automotive process. This milestone underscores Cadence's commitment to delivering high-performance, automotive-grade IP solutions that meet the stringent requirements of next-generation automotive and high-performance computing applications.
40G UCIe IP Advantages for AI Applications
For AI workloads to be processed reliably at a fast rate, the die-to-die interface in multi-die designs must be robust, low latency, and most importantly high bandwidth. This article outlines the need for 40G UCIe IP in AI data center chips leveraging multi-die designs.
Frequently asked questions about UCIe IP cores
What is UCIe Chiplet PHY & Controller?
UCIe Chiplet PHY & Controller is a UCIe IP core from Innosilicon Technology Ltd listed on Semi IP Hub.
How should engineers evaluate this UCIe?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this UCIe IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.