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This article shares our experience using Google’s FlatBuffers library as a memory subsystem stress test on the Andes AX46MPV RISC-V core.
Vendor:
Ventana Micro Systems Inc.
Category:
CPU
RISC-V System IP
Streamline Ventana technology integration into high-performance systems, fully leveraging third-party IP, while applying RISC-V s…
Overview
Streamline Ventana technology integration into high-performance systems, fully leveraging third-party IP, while applying RISC-V simplifying system principles.
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Interrupts
RISC-V AIA (Advanced Interrupt Architecture) builds upon PCIe MSI (Message-Signaling Interrupts) to reduce the complexity of the interrupt implementation. Using memory-mapped transactions removes the need for specialized interrupt protocols and sideband interrupt signaling networks. Ventana CPUs, including the Veyron V1 and V2, include the AIA IMSIG (Incoming Message-Signaled Interrupt Controller) function within the CPU cluster to process interrupts within each CPU core. The APLIC IP can be used if there are wired interrupts that need to be converted to MSI transactions. -
Debug & Trace
RISC-V debug & trace utilizes a memory-mapped architecture to remove the need for specialized protocols and sideband trace buses. CPU traces are sent to main memory with a timestamp using a unified system timebase (mtime) established at startup. CPU and system traces can then be read out from memory over any high-speed IO interface and combined using the timestamps to stitch together the system context. -
Memory Protection & Translation
Ventana utilizes RISC-V architecture features that allow protection at the source of a transaction, compared to a destination approach as found in some common legacy architectures. Source side allows a richer and more fine-grained set of protection constructs compared to a destination approach. The ePMP (enhanced Physical Memory Protection) functionality is implemented within Ventana’s CPU, including the Veyron V1 and V2, for CPU-based transitions, while the IOMMU protects against device-based transactions.
Ventana System IP
- IOMMU
IOMMU performs the corollary set of functions for device-based transactions as the CPU’s MMU functionality. This allows connected devices to be virtualized and operate within a unified virtual memory space with CPUs, including Veyron V1 and V2, while protecting the system from invalid device transactions. - APLIC
APLIC (Advanced Platform Level Interrupt Controller) can be used in systems that need to support wired interrupt signals. The APLIC controller converts between wired interrupts and their corresponding MSI memory-mapped transactions sent within a RISC-V AIA interrupt architecture. - CPX
CPX (Cluster Proxy) enables Ventana compute chiplets to be seamlessly interfaced to a companion Hub SoC through a lightweight D2D transport of AMBA protocols. The CPX block integrates within the Hub SoC and bridges between the D2D PHY transport and the “proxy” CPU cluster interface connections within the Hub. The interface profile is detailed on the Ventana CPU product pages since it is unique to each product.
Specifications
Identity
Part Number
RISC-V System IP
Vendor
Ventana Micro Systems Inc.
Type
Silicon IP
Compute
CPU Architecture
RISC-V
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
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Frequently asked questions about CPU IP cores
What is RISC-V System IP?
RISC-V System IP is a CPU IP core from Ventana Micro Systems Inc. listed on Semi IP Hub.
How should engineers evaluate this CPU?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this CPU IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.