Xilinx, Inc. IP Cores

Xilinx offers an integrated 100 Gigabit per second (Gbps) Ethernet Media Access Controller (MAC), Physical Coding Sublayer (PCS),…

• Ethernet

The Xilinx® UltraScale+ FPGA Integrated Block for PCI Express® solution IP core is a high-bandwidth, scalable, and reliable seria…

• PCI Express

Xilinx offers an integrated 100 Gigabit per second (Gbps) Ethernet Media Access Controller (MAC) and Physical Coding Sublayer (PC…

• Ethernet

The Xilinx® LogiCORE™ IP UltraScale™ architecture integrated IP core for Interlaken is a scalable chip-to-chip interconnect proto…

• Interlaken

The customizable System Integrated Logic Analyzer (System ILA) IP core is a logic analyzer which can be used to monitor the inter…

• Debug Trace

Xilinx provided utility function to simplify design in Vivado IP Integrator.

• Control Logic

The RLD3 Controller gives you the ability to design for Reduced Latency DRAM while maintaining high performance and density.

• Controller

This Physical Layer core gives you the ability to simultaneously read and write on every rising and falling edge.

• SRAM

This Physical Layer core gives you the ability to simultaneously read and write on every rising and falling edge.

• SRAM

The Phase Locked Loop primitive in Virtex-5 FXT parts is used to generate multiple clocks with defined phase and frequency relati…

• PLL

The Xilinx MIPI DSI (Display serial interface) Transmitter Subsystem implements the Mobile Industry Processor Interface (MIPI) ba…

• MIPI

The Xilinx MIPI CSI2 Receiver Subsystem and MIPI CSI 2 Transmitter Subsystems implement the Mobile Industry Processor Interface (…

• MIPI

MicroBlaze™ is a 32-bit RISC soft processor core that can be used with soft peripherals to design embedded systems in Xilinx FPGA…

• MCU

The LogiCORE In-System IBERT IP enables 2D eye scans of Ultrascale™/Ultrascale+™ transceivers to be performed the in Vivado® Seri…

• Test / Debug

The HARD_TEMAC described in this document has been designed incorporating the applicable features described in IEEE Std.

• Ethernet

The Xilinx® LogiCORE™ IP Debug Bridge core is a controller which provides a mechanism to establish a communication channel for de…

• Protocol Bridge

The Xilinx DDR4 controller is high performance (2667Mbps in UItraScale+) and supports a wide range of configurations from low cos…

• Controller
• DDR4

The Xilinx DDR3 controller is high performance (2133Mbps in UItraScale) with support for lower power DDR3L as well as UDIMMs, SOD…

• Controller
• DDR3

Xilinx provided utility function to simplify design in Vivado IP Integrator.

• Control Logic

Xilinx provided utility function to simplify design in Vivado IP Integrator.

• Control Logic