Xilinx, Inc. IP Cores

Forward Error Correction (FEC) codes such as Low Density Parity Check (LDPC) codes provide a means to control errors in data tran…

• Channel Coding

The IEEE 802.3 Clause 74 FEC IP core performs the functions of the IEEE Clause 74 FEC, sometimes known as “KR FEC”, as described …

• Channel Coding

The Xilinx® 10G Ethernet TSN solution provides a 10 Gigabit per second (Gbps) Ethernet Media Access Controller integrated with a …

• Ethernet

Xilinx® offers the 25 Gigabit IEEE 802.3by Reed-Solomon Forward Error Correction (RS-FEC) IP core for data center and enterprise …

• Channel Coding

The ability to purchase AXI BFM has been discontinued as of December 1, 2016.

• Protocol Bridge

Clock Verification IP can be used to generate clock signals in testbench.

• Verification IP

The LogiCORE™ ChipScope™ Pro Integrated Bit Error Ratio Tester (IBERT) core for Virtex®-6 FPGA GTH transceivers is a customizable…

• Test / Debug

The AXI VIP can be used to verify connectivity and basic functionality of AXI masters and AXI slaves with the custom RTL design f…

• Verification IP

The AXI Stream VIP can be used to verify connectivity and basic functionality of AXI Stream masters and AXI Stream slaves with th…

• Verification IP

The Xilinx® LogiCORE™ AXI Sideband Formatter Utility is used to insert and recover sideband information onto the AXI USER signals…

• Protocol Bridge

The Xilinx® LogiCORE™ AXI Firewall IP is designed to protect AXI DMA from hangs and protocol violations downstream of it that may…

• IPsec / TLS

The Xilinx® LogiCORE™ IP I2S Transmitter and Receiver cores are soft IP cores in Xilinx Vivado design suite which make it easy to…

• I2S

Converts Avalon Master Endpoints to AXI for seamless interconnection and integration

• Protocol Bridge

Xilinx provides an 100M/1G TSN Subsystem to accelerate time to market and drive the convergence of low latency deterministic Indu…

• Ethernet

The 1G and 10G Switching Ethernet Subsystem dynamically switches an Ethernet Media Access Controller (MAC) between 1G or 10G phys…

• Ethernet

Xilinx provides the Processing System IP Wrapper for the Zynq®-7000 to accelerate your design and its configuration for your embe…

• CPU

Xilinx provides the Processing System IP Wrapper for the Zynq UltraScale+ MPSoC to accelerate your design and its configuration f…

• CPU

The Xilinx® LogiCORE™ IP HMC Controller implements a high performance, configurable HMC host controller for user to interconnect …

• Controller

The Xilinx® LogiCORE™ IP Video Mixer enables users to mix video layers.

• Video Processing

Xilinx provided utility function to simplify design in Vivado IP Integrator.

• Control Logic