Xilinx, Inc. IP Cores

The LogiCORE™ ChipScope™ Pro Integrated Bit Error Ratio Tester (IBERT) core for Virtex®-6 FPGA GTH transceivers is a customizable…

• Test / Debug

The Xilinx® CAN FD IP core is ideally suited for automotive and industrial applications such as automotive gateways, body control…

• CAN / CAN-FD / CAN-XL

The LogiCORE™ IP AXI4-Lite IP Interface (IPIF) is a part of the Xilinx family of ARM® AMBA® AXI control interface compatible prod…

• Protocol Bridge

The Xilinx® LogiCORE™ IP AXI SmartConnect core connects one or more AXI memory-mapped master devices to one or more memory-mapped…

• Network-On-Chip

The AXI PCIe® Gen 3 core provides an interface between the AXI4 interface and the Gen 3 PCI Express (PCIe) silicon hard core.

• PCI Express

The AXI MCDMA facilitates large data migration, offloading the task from the embedded processor.

• DMA

The Xilinx® LogiCORE™ AXI AMM Bridge IP core connects Avalon bridge slave IPs with AXI interface masters.

• Protocol Bridge

Xilinx provides a 7 Series FPGA solution for PCI Express® (PCIe) to configure the 7 Series FPGA Integrated Block for PCIe and inc…

• PCI Express

DO-DI-PCIX64-VE rolls the Initiator/Target for PCI ™/PCI-X ™, 32-bit Initiator/Target for PCI and 64-bit Initiator/Target for PCI…

• PCI

Xilinx® offers the 50 Gigabit Reed-Solomon Forward Error Correction (RS-FEC) IP core for data center and enterprise applications.

• Channel Coding

The Xilinx® LogiCORE™ IP 40G/50G Ethernet solution provides a 40 Gigabit or 50 Gigabit per second (Gbps) Ethernet Media Access Co…

• Ethernet

The LTE PUCCH Receiver LogiCORE™ IP core provides the receive functionality required for the LTE Physical Uplink Control CHannel …

• Channel Coding

The Xilinx® LogiCORE™ 32G Fibre Channel (32GFC) RS-FEC IP core implements the Reed-Solomon Forward Error Correction (RS-FEC) subl…

• Channel Coding

Xilinx® offers the 100 Gigabit IEEE 802.3bj Reed-Solomon Forward Error Correction (RS-FEC) IP core for data center and enterprise…

• Channel Coding

No charge paramaterizable core which utilizes the serial I/O transceivers available in the Kintex® UltraScale™, Virtex® UltraScal…

• Ethernet

The Xilinx® Video Processing Subsystem provides configurable video processing pipe handling resolutions up to 4K.

• Vision Subsystem

The Xilinx® LogiCORE™ IP UltraScale™ architecture integrated IP core for Interlaken is a scalable chip-to-chip interconnect proto…

• Interlaken

Xilinx offers an integrated 100 Gigabit per second (Gbps) Ethernet Media Access Controller (MAC) and Physical Coding Sublayer (PC…

• Ethernet

Xilinx provides a PCI Express Gen3 Integrated block for PCI Express® (PCIe) in the UltraScale™ family of FPGAs.

• PCI Express

The LogiCORE™ IP UltraScale™ FPGAs Transceivers Wizard generates customized HDL to configure the UltraScale FPGA on-chip serial t…

• Multi-Protocol PHY