Vendor: Xilinx, Inc. Category: PCI Express

UltraScale+ Device Integrated Block for PCI Express (PCIe)

The Xilinx® UltraScale+ FPGA Integrated Block for PCI Express® solution IP core is a high-bandwidth, scalable, and reliable seria…

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Overview

The Xilinx® UltraScale+ FPGA Integrated Block for PCI Express® solution IP core is a high-bandwidth, scalable, and reliable serial interconnect building block solution for use with UltraScale+™ devices. The Integrated Block for PCI Express (PCIe) solution supports 1-lane, 2-lane, 4-lane, 8-lane, and 16-lane Endpoint configurations, including Gen1 (2.5 GT/s), Gen2 (5.0 GT/s) and Gen3 (8 GT/s) speeds. This solution supports the AXI4-Stream.

Key features

  • Designed to PCI Express Base Specification 3.1
  • PCI Express Endpoint, Legacy Endpoint or Root Port Port Modes
  • x1, x2, x4, x8 or x16 link widths
  • Gen1, Gen2 and Gen3 link speeds
  • PHY only mode available
  • AXI4 Streaming Interface to customer logic
    • Configurable 64-bit/128-bit/256-bit/512-bit data path widths
    • Four Independent Initiator/Target, Request/Completion Streams
  • Parity protection on internal logic data paths and data interfaces
  • Advanced Error Reporting (AER) and End-to-End CRC (ECRC)

Specifications

Identity

Part Number
UltraScale+ Device Integrated Block for PCI Express (PCIe)
Vendor
Xilinx, Inc.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Xilinx, Inc.
HQ: USA
Contact Xilinx, Inc.

Learn more about PCI Express IP core

How to design FPGA-based advanced PCI Express endpoint solutions

Currently dominating the desktop PC motherboard and graphics markets, the PCI Express protocol is poised to supplant PCI and PCI-X interface as the dominant high-bandwidth interconnect for the server, enterprise, mobile, workstation, networking, communica

Repeatable results with design preservation

Increasingly, FPGA designs are no longer just the 'glue logic' of the past; they are becoming more complex every year, often incorporating challenging such as PCI Express cores. Time spent trying to maintain timing in these modules is not only frustrating, but often unproductive as well. The design preservation flow solves this issue by allowing the customer to meet timing on the critical module(s) of the design and then reuse the implementation results in future iterations.

Frequently asked questions about PCIe IP cores

What is UltraScale+ Device Integrated Block for PCI Express (PCIe)?

UltraScale+ Device Integrated Block for PCI Express (PCIe) is a PCI Express IP core from Xilinx, Inc. listed on Semi IP Hub.

How should engineers evaluate this PCI Express?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PCI Express IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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