How to simplify power design development and evaluation for FPGA-based systems
Validation of power supply voltage at the FPGA; real-time monitoring of Vccint power consumption; realistic power estimates using accurate on-die temperature measurement.
Vendor:
Xilinx, Inc.
Category:
Test / Debug
In-System IBERT IP
The LogiCORE In-System IBERT IP enables 2D eye scans of Ultrascale™/Ultrascale+™ transceivers to be performed the in Vivado® Seri…
Overview
The LogiCORE In-System IBERT IP enables 2D eye scans of Ultrascale™/Ultrascale+™ transceivers to be performed the in Vivado® Serial I/O Analyzer tool. It utilizes data from the user design to plot the eye scans of transceivers in real-time while they interact with the rest of the system. This IP can be integrated with the user logic in the design or Xilinx transceiver-based IPs such as GT Wizard, Aurora, etc. This document details the IP functionality and different ways for adding it to the user design.
Key features
- Provides a communication path to the Vivado Serial I/O Analyzer feature
- Utilizes data from user design to scan and measure the eye
- Provides access to DRP and selected Transceiver ports
- Requires a system clock that can be sourced from a pin or one of the enabled transceivers
Specifications
Identity
Part Number
In-System IBERT IP
Vendor
Xilinx, Inc.
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
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Frequently asked questions about SerDes Test / Debug IP cores
What is In-System IBERT IP?
In-System IBERT IP is a Test / Debug IP core from Xilinx, Inc. listed on Semi IP Hub.
How should engineers evaluate this Test / Debug?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Test / Debug IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.