AMD Receives All Necessary Approvals for Proposed Acquisition of Xilinx
AMD (NASDAQ: AMD) today announced that it has received approval from all necessary authorities to proceed with the acquisition of Xilinx, Inc. (NASDAQ: XLNX).
Vendor:
Xilinx, Inc.
Category:
Protocol Bridge
Debug Bridge
The Xilinx® LogiCORE™ IP Debug Bridge core is a controller which provides a mechanism to establish a communication channel for de…
Overview
The Xilinx® LogiCORE™ IP Debug Bridge core is a controller which provides a mechanism to establish a communication channel for debug cores with runtime software. The Debug Bridge usage can be classified into two categories: Tandem with Field Updates and Xilinx Virtual Cable (XVC). These two categories provide the means for communicating with the debug IP (including Memory IP) that is in the design. The Tandem with Field Updates flow allows you to download new functionality into a device over the PCIe® link after the device is initially configured through the Tandem PROM/PCIe. The XVC flow allows you to use debug cores and debug the design over non JTAG interface (for example, Ethernet/PCIe).
Key features
- Tandem with Field Updates and Partial Reconfiguration Solution – User selectable mode From_BSCAN_to_Debug is used to add a Debug Bridge instance in each Reconfigurable Module which would connect to debug cores like ILA, VIO, Memory IP, and JTAG2AXI
- Xilinx Virtual Cable (XVC) Solution – Three modes are supported:
- User selectable mode From_AXI_to_BSCAN is used to add a Debug Bridge instance in the design with an Ethernet/PCIe master. This mode is a slave to Ethernet/PCIe master while connecting to debug cores like ILA, VIO, Memory IP, and JTAG2AXI in the same chip
- User selectable mode From_AXI_to_JTAG is used to add a Debug Bridge instance in the design with an Ethernet/PCIe master. This mode is a slave to Ethernet/PCIe master while bringing out the JTAG pins out of the FPGA through I/O pins. This mode is mainly used to debug design on another board over XVC.
- User selectable mode From_JTAG_to_BSCAN is used to add a Debug Bridge instance to debug the designs over soft Test Access Port (TAP) controller.
Specifications
Identity
Part Number
Debug Bridge
Vendor
Xilinx, Inc.
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
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Frequently asked questions about Protocol Bridge IP cores
What is Debug Bridge?
Debug Bridge is a Protocol Bridge IP core from Xilinx, Inc. listed on Semi IP Hub.
How should engineers evaluate this Protocol Bridge?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Protocol Bridge IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.