Designing DDR3 SDRAM controllers with today's FPGAs
This article outlines the major differences between DDR3 and DDR2 SDRAM architecture and reviews them in the context of an FPGA-based reference design tested in hardware at 800 Mbps.
Vendor:
Xilinx, Inc.
Category:
DDR
RLD3 Controller
The RLD3 Controller gives you the ability to design for Reduced Latency DRAM while maintaining high performance and density.
Overview
The RLD3 Controller gives you the ability to design for Reduced Latency DRAM while maintaining high performance and density. Build the RLD3 Controller with the Memory Interface GUI to get a complete set of unencrypted RTL, constraints, simulation files, and scripts.
Key features
- x9, x18, x36 device targets
- Up to 2.24Gb density
- Source code delivery in Verilog
Specifications
Identity
Part Number
RLD3 Controller
Vendor
Xilinx, Inc.
Type
Silicon IP
Controller / PHY
Controller
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
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Frequently asked questions about DDR Interface IP
What is RLD3 Controller?
RLD3 Controller is a DDR IP core from Xilinx, Inc. listed on Semi IP Hub.
How should engineers evaluate this DDR?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.