AMD Receives All Necessary Approvals for Proposed Acquisition of Xilinx
AMD (NASDAQ: AMD) today announced that it has received approval from all necessary authorities to proceed with the acquisition of Xilinx, Inc. (NASDAQ: XLNX).
Vendor:
Xilinx, Inc.
Category:
SRAM
QDRIV SRAM Core
This Physical Layer core gives you the ability to simultaneously read and write on every rising and falling edge.
Overview
This Physical Layer core gives you the ability to simultaneously read and write on every rising and falling edge. QDRIV is a low-latency SRAM-based standard, used in cache coherent systems, data and packet buffering, lookup tables, and other networking applications.
Key features
- x18, x36 device targets
- Very low latency reads
- 2 word burst support
- Reliable and predictable transaction times
- Separate read and write busses
- Source code delivery in Verilog
Specifications
Identity
Part Number
QDRIV SRAM Core
Vendor
Xilinx, Inc.
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
Learn more about SRAM IP core
AMD Acquisition of Xilinx Heats Up Competition with Intel
AMD’s acquisition of Xilinx in an all-stock transaction valued at $35 billion promises to raise the stakes in the second-ranked CPU maker’s competition with Intel.
AMD and Xilinx Provide Update Regarding Expected Timing of Acquisition Close
AMD (NASDAQ: AMD) and Xilinx, Inc. (NASDAQ: XLNX) today released the following statement related to the status of global regulatory approvals for AMD’s proposed acquisition of Xilinx.
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Frequently asked questions about SRAM IP cores
What is QDRIV SRAM Core?
QDRIV SRAM Core is a SRAM IP core from Xilinx, Inc. listed on Semi IP Hub.
How should engineers evaluate this SRAM?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this SRAM IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.