Vendor: Xilinx, Inc. Category: MIPI

MIPI DSI TX Controller Subsystem

The Xilinx MIPI DSI (Display serial interface) Transmitter Subsystem implements the Mobile Industry Processor Interface (MIPI) ba…

Overview

The Xilinx MIPI DSI (Display serial interface) Transmitter Subsystem implements the Mobile Industry Processor Interface (MIPI) based display interface.  The Display Serial Interface Specification defines protocols between a host processor and peripheral devices using a D-PHY physical interface. The DSI specification builds on existing specifications by adopting pixel formats and command set defined in MIPI Alliance specifications for Display Pixel Interface 2 (DPI-2) and Display Command Set (DCS) 

Key features

  • Compliant with the MIPI DSI  Interface Specification, rev. 1.3
  • Standard PPI interface towards D-PHY
  • 1-4 Lane Support
  • Maximum Data Rate – 1.5 Gigabits per second
  • Supports all mandatory data types
  • Virtual channel (1 to 4)Programmable EoTp generation support
  • Low Power (LP) and Ultra Low Power(ULP) mode generation
  • Multilane interoperability
  • ECC generation for packet header
  • CRC generation for data bytes(Can be Optional)
  • Pixel byte conversion based on data format
  • AXI4-Lite interface to access core registers
  • Compliant with UG934 for input video stream

Specifications

Identity

Part Number
EF-DI-MIPI-DSI-TX
Vendor
Xilinx, Inc.
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: USA

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Frequently asked questions about MIPI IP cores

What is MIPI DSI TX Controller Subsystem?

MIPI DSI TX Controller Subsystem is a MIPI IP core from Xilinx, Inc. listed on Semi IP Hub.

How should engineers evaluate this MIPI?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this MIPI IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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