The Fraunhofer Institute for Integrated Circuits (IIS) offers core components for ASIC and FPGA solutions. The cores are developed by Fraunhofer IIS in Erlangen, Germany and selected partners. Over 25 years of system and design know-how, analog and digital design experience, and the needs of our customers have influenced the methodology to develop these cores.
Each core has been verified with sophisticated test procedures at Fraunhofer IIS before it is offered to the customers. As a result, the cores are of high quality and proven technology. Many components are parameterizable and allow the designer to tailor each component to the needs of the application. Therefore, using our components saves lots of design and verification effort.
11 Bit 100 kS/s Ultra-Low Power SAR ADC on GlobalFoundries 22FDSOI
The ADC IP is a general-purpose successive approximation converter for low-power medium resolution applications.
Ultra-Low-Power 6-13 Bit 1-10 kS/s 1.9 µW SAR ADC on XFAB XT018
The IP consists of a Successive Approximation Register (SAR) architecture ADC using charge-redistribution technique.
Ultra-Low-Power 6-13 Bit 0.5-10 KS/s 10μW Analog-Frontend on XFAB XT018
The Analog-Frontend (AFE) IP consists of programmable current and voltage preamplifier followed by a Successive Approximation Reg…
16 Bit 10 kS/s Incremental Delta-Sigma ADC on AMS H35
On the one hand, incremental delta-sigma modulators are able to convert DC and multiplexed input signals as known from Nyquist AD…
15 Bit 8 kS/s Sigma-Delta ADC on XFAB XH018
The ADC IP is a general-purpose sigma-delta converter and it is configurable for conversion speed and power consumption with adap…
12-Bit 1 MS/s DAC with voltage output on AMS C18
The IP consists of a 12 bit current steering DAC.
Ultra-low power RF receiver / WakeUp receiver
RFicient®Basic, Ultra-Low-Power WakeUp Receiver – this IC solution will allow customers to optimize the power consumption for i.e.
12 Bit 20 MS/s Pipeline ADC on XFAB XH035
This pipelined ADC can be applied for up to 20MSps sampling frequencies.
10 Bit 40 MS/s Pipeline ADC on AMS C18
The IP consists of a 10 bit 40 MS/s pipeline ADC.
12 Bit 40 MS/s Pipeline ADC on XFAB XH018
This pipelined ADC can be applied for up to 40MSps sampling rates with on-chip track&hold block or continuous signal sampling.
8 Bit 6 GS/s Current Steering DAC on Fujitsu 55 nm CS250L
The IP consists of an 8 bit current steering DAC clocked externally for 4 - 6 GS/s.
7 Bit 6 GS/s Folding ADC on Fujitsu 55 nm CS250L
The IP consists of a 7 bit monolithic folding ADC clocked externally for 6 GS/s.
15 Bit 192 kS/s Sigma-Delta ADC on XFAB XH018
The ADC IP is a general-purpose sigma-delta converter and it is configurable for conversion speed and power consumption with adap…
12 Bit 54 kS/s Cyclic ADC on XFAB XH018
This cyclic ADC, based on redundant-signed-digit (RSD) conversion, is optimized for power efficiency and high accuracy.
12 Bit 17 kS/s Cyclic ADC on XFAB XH018
This cyclic ADC, based on redundant-signed-digit (RSD) conversion, is optimized for power efficiency and high accuracy.
16 Bit 13 kS/s Cyclic ADC on XFAB XH018
This cyclic ADC, based on redundant-signed-digit (RSD) conversion, is optimized for power efficiency and high accuracy.