This pipelined ADC can be applied for up to 40MSps sampling rates with on-chip track&hold block or continuous signal sampling.
This pipelined ADC can be applied for up to 40MSps sampling rates with on-chip track&hold block or continuous signal sampling.
This fully differential ADC is designed to convert full swing (-1V to +1 V) input signals as well as unipolar input signals with 12 bits resolution. Furthermore the input voltage signals can exceed the 1.8V voltage range by using optional 3.3V input stage.
The ADC IP includes reference voltage generation and buffers and optional high-precision trimmed bandgap reference.
The ADC is silicon proven in Automotive mass production using the XFAB XH018 process. Measurement results and samples are available.
Fraunhofer IIS provides a detailed documentation and support for the IP integration.
Modifications, extensions and technology ports of the IP are available on request.
Note: some files may require an NDA depending on provider policy.
12 Bit 40 MS/s Pipeline ADC on XFAB XH018 is a ADC IP core from Fraunhofer Institute Integrated Circuits and Systems (IIS) listed on Semi IP Hub.
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this ADC IP.
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.
