The IP consists of an 8 bit current steering DAC clocked externally for 4 - 6 GS/s.
The IP consists of an 8 bit current steering DAC clocked externally for 4 - 6 GS/s. The differential output signal of maximum +/- 800 mV is driven onto a load impedance of 100 Ohm and can be calibrated within a range of +/- 25 % of its nominal value to adjust to load conditions.
The IP needs an external clock with high accuracy and low periodic jitter, because the clock jitter influences the dynamic behavior of the converter.
The digital input word of 8 bits is taken as a 4x parallel bus. A data clock provides the frequency; phase sync for the data interface is done via an internal FIFO. The DAC is silicon evaluated in Fujitsu 55 nm CS250L technology.
Fraunhofer IIS provides a detailed documentation and support for the IP integration. Modifications, extensions and technology ports of the IP are available on request.
Note: some files may require an NDA depending on provider policy.
8 Bit 6 GS/s Current Steering DAC on Fujitsu 55 nm CS250L is a DAC IP core from Fraunhofer Institute Integrated Circuits and Systems (IIS) listed on Semi IP Hub.
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DAC IP.
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