Vendor: Fraunhofer Institute Integrated Circuits and Systems (IIS) Category: DAC

8 Bit 6 GS/s Current Steering DAC on Fujitsu 55 nm CS250L

The IP consists of an 8 bit current steering DAC clocked externally for 4 - 6 GS/s.

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Overview

The IP consists of an 8 bit current steering DAC clocked externally for 4 - 6 GS/s. The differential output signal of maximum +/- 800 mV is driven onto a load impedance of 100 Ohm and can be calibrated within a range of +/- 25 % of its nominal value to adjust to load conditions.

The IP needs an external clock with high accuracy and low periodic jitter, because the clock jitter influences the dynamic behavior of the converter.

The digital input word of 8 bits is taken as a 4x parallel bus. A data clock provides the frequency; phase sync for the data interface is done via an internal FIFO. The DAC is silicon evaluated in Fujitsu 55 nm CS250L technology.

Fraunhofer IIS provides a detailed documentation and support for the IP integration. Modifications, extensions and technology ports of the IP are available on request.

Key features

  • Resolution: 8 bit 
  • Conversion rate: 4 to 6 GS/s 
  • Power consumption: < 350 mW
  • Signal-to-Noise: > 43 dB (up to 3 GHz)
  • Spurious-free dynamic range: > 46 dB (up to 3 GHz)
  • Differential  output voltage:   +/- 800 mV (100 Ω load) 
  • Supply voltage core: 1.2 V +/- 5 %
  • Supply voltage peri:  3.3 V +/- 5 % 
  • Operating clock: 4 to 6 GHz 
  • Temperature range:- 40 oC to 125 oC

Block Diagram

DAC08b006GS055nm block diagram

Benefits

  • Low design risk due to silicon evaluated design
  • Robust operation across full temperature range from - 40 °C up to 125 °C
  • Tunability of full-range voltage provides adaptable  amplitude while keeping full resolution

What’s Included?

  • GDSII data
  • Simulation model
  • Documentation
  • Integration support

Specifications

Identity

Part Number
DAC08b006GS055nm
Vendor
Fraunhofer Institute Integrated Circuits and Systems (IIS)
Type
Silicon IP

Analog

Resolution bits
8 Bit

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact Fraunhofer Institute Integrated Circuits and Systems (IIS)

Learn more about DAC IP core

Specifying a PLL Part 1: Calculating PLL Clock Spur Requirements from ADC or DAC SFDR

In high end RF systems, such as 5G radios, the requirements are so stringent that the source of this strongest unwanted tone can be the PLL. This article outlines how spurs in the input clock to the ADC or DAC may limit the SFDR. This in turn will set the requirements for the spurs for the input clock (from a PLL), in order to achieve a specific SFDR.

Frequently asked questions about DAC IP cores

What is 8 Bit 6 GS/s Current Steering DAC on Fujitsu 55 nm CS250L?

8 Bit 6 GS/s Current Steering DAC on Fujitsu 55 nm CS250L is a DAC IP core from Fraunhofer Institute Integrated Circuits and Systems (IIS) listed on Semi IP Hub.

How should engineers evaluate this DAC?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DAC IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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