DAC 2024 - Showcasing the future of RISC-V through EDA
Brett Cline, Codasip
Vendor:
Fraunhofer Institute Integrated Circuits and Systems (IIS)
Category:
DAC
12-Bit 1 MS/s DAC with voltage output on AMS C18
The IP consists of a 12 bit current steering DAC.
Overview
The IP consists of a 12 bit current steering DAC. The DAC is connected to a transimpedance amplifier(TIA) in order to provide a voltage output signal. The amplifier can be adapted for different applications to optimize for performance, power consumption or output load of the IP.
The digital input data is saved to an internal register and provided immediately to the output.
The IP uses a single current reference input. A matching current reference cell can be provided. 7 bit gain and offset trimming is included to adapt for process variations.
The DAC is silicon proven using the AMS C18 process. Measurement results are available from evaluation and volume production. One application of the IP is an industrial sensor ASIC for safety critical applications.
Fraunhofer IIS provides a detailed documentation and support for the IP integration.
Modifications, extensions and technology ports of the IP are available on request.
Key features
- Resolution: 12 bit
- Conversion rate: 1 MS/s
- Power consumption: 15 mW @ 3.3 V
- Integral non-linearity: +/- 1.5 LSB
- Diff. non-linearity: +/- 0.7 LSB
- Supply voltage: 3.0 V – 3.6 V
- Operation clock: 0 – 1 MHz
- Output voltage range: 1.8 V – 2.8 V
- Output load: >= 100 Ohm
- Temperature range: -40 °C – 125 °C
Block Diagram
DAC12b001MS180nm block diagram
Benefits
- Low design risk due to silicon proven design
- Easy to use input due to integrated output buffer
- Robust operation across full temperature range from -40 °C up to 125 °C
- Simple integration due to integrated reference drivers and reference trimming DAC
Applications
- Automation
- Industrial
What’s Included?
- GDSII data
- Simulation model
- Documentation
- Silicon validation report
- Integration support
Specifications
Identity
Part Number
DAC12b001MS180nm
Vendor
Fraunhofer Institute Integrated Circuits and Systems (IIS)
Type
Silicon IP
Analog
Resolution bits
12 Bit
Files
Note: some files may require an NDA depending on provider policy.
Provider
Learn more about DAC IP core
Making the most of the 60th DAC
Brett Cline, Codasip
DAC 2022 - Is it too risky not to adopt RISC-V?
Brett Cline, Codasip
Specifying a PLL Part 1: Calculating PLL Clock Spur Requirements from ADC or DAC SFDR
In high end RF systems, such as 5G radios, the requirements are so stringent that the source of this strongest unwanted tone can be the PLL. This article outlines how spurs in the input clock to the ADC or DAC may limit the SFDR. This in turn will set the requirements for the spurs for the input clock (from a PLL), in order to achieve a specific SFDR.
DAC: The View from Wall Street
DAC Panelists Discuss Emulation's Versatility & Various Use Models
Lauro Rizzatti, Verification Consultant
Frequently asked questions about DAC IP cores
What is 12-Bit 1 MS/s DAC with voltage output on AMS C18?
12-Bit 1 MS/s DAC with voltage output on AMS C18 is a DAC IP core from Fraunhofer Institute Integrated Circuits and Systems (IIS) listed on Semi IP Hub.
How should engineers evaluate this DAC?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DAC IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.