Overview
The IP consists of a 7 bit monolithic folding ADC clocked externally for 6 GS/s.
The differential input signal of maximum +/- 450 mV is ac-coupled to the input. Lower cut off frequency is well below 500 kHz.
The ADC is calibrated internally after reset to increase precision. The calibration can be disabled and can also be triggered manually.
The reference voltage is either derived from the 1.2 V supply or can alternatively be provided externally.
The IP needs an external clock with high accuracy and low jitter, because the clock jitter may influence the dynamic features of the converter. This clock is used as the sampling clock.
The digital output word of 7 bits is provided as a 4x parallel bus together with the clock.
The ADC is silicon evaluated in Fujitsu 55 nm CS250L technology.
Fraunhofer IIS provides a detailed documentation and support for the IP integration. Modifications, extensions and technology ports of the IP are available on request.
Learn more about ADC IP core
This paper introduces a novel closed-loop testing methodology for efficient linearity testing of high-resolution Successive Approximation Register (SAR) Analog-to-Digital Converters (ADCs). Existing test strategies, including histogram-based approaches, sine wave testing, and model-driven reconstruction, often rely on dense data acquisition followed by offline post-processing, which increases overall test time and complexity.
Analog to digital converters have three key input ports along with data output ports as per digital resolution requirements. These inputs ports are Analog Signal, Reference and Clock. If we compare across most of the converter architectures then clock frequency is directly related to output data rate and latency of the data conversion.
The growing availability of digital ICs like microcontrollers, microprocessors, and field-programmable gate arrays (FPGAs) allows developers to use complex digital processing techniques rather than analog signal conditioning. For this reason, analog-to-digital converters (ADCs) have become a widely-used component in mixed-signal circuits.
In high end RF systems, such as 5G radios, the requirements are so stringent that the source of this strongest unwanted tone can be the PLL. This article outlines how spurs in the input clock to the ADC or DAC may limit the SFDR. This in turn will set the requirements for the spurs for the input clock (from a PLL), in order to achieve a specific SFDR.
Power-sensitive applications such as Internet-of-Things (IoT) require a comprehensive power savings strategy within the system-on-chip (SoC). Techniques relying solely on the use of traditional power down modes and low supply voltage may not be enough to achieve the required power targets. The analog block is often assumed to be too sensitive and not compatible with aggressive power management techniques.
When continuously running a high speed ADC, it can be a challenge to deal with the firehose of raw data available at the output. To use City Semiconductor’s 2.5 GS/s 12-bit ADC, for example, 30 gigabits per second of data have to be accepted.
