Vendor: Fraunhofer Institute Integrated Circuits and Systems (IIS) Category: ADC

Ultra-Low-Power 6-13 Bit 1-10 kS/s 1.9 µW SAR ADC on XFAB XT018

The IP consists of a Successive Approximation Register (SAR) architecture ADC using charge-redistribution technique.

13 Bit X-FAB 180nm XT018 Available on request View all specifications

Overview

The IP consists of a Successive Approximation Register (SAR) architecture ADC using charge-redistribution technique. The ADC IP is configurable regarding resolution (6-13 bit) and sample rate (up to 10kS/s) and power consumption down to 1.9 µW. The input voltage range is quasi-rail-to-rail guaranteeing more than + 1.7 V@ 1.8V power supply. An optional calibration technique can be applied to compensate degraded mismatch behavior of technology capacitors.

The ADC IP is applied for industrial and automotive ASIC products.

The ADC IP is silicon evaluated using the XFAB XT018 process. Measurement results and samples are available. The ADC IP was migrated to GF 22FDX and TSMC BCD180 technology with sampling rates up to 2MS/s.

Fraunhofer IIS/EAS provides a detailed documentation and support for the IP integration. Modifications, extensions and technology ports of the IP are available on request.

Key features

  • Resolution: 6 - 13 bit 
  • Conversion rate: up to 10 kS/s 
  • Power consumption: 1.9 µW @ 0.5kS/s
  • ENOB: 12.6 bit 
  • Supply voltage: 1.8 V 
  • Operation clock: 140 kHz
  • Differential input: +-1.7 V 
  • Silicon area: 0.09 mm2

Block Diagram

ADC13b010kS180nm block diagram

Benefits

  • Low design risk due to silicon evaluated design
  • Easy to use input due to integrated input buffer
  • Selectable power consumption due to integrated automatic power-down function
  • Task dependent selectable resolution
  • Flexible use due to single-conversion and continous-conversion mode

What’s Included?

  • GDSII data
  • Simulation model
  • Documentation
  • Silicon validation report
  • Integration support

Silicon Options

Foundry Node Process Maturity
X-FAB 180nm XT018 Available on request

Specifications

Identity

Part Number
ADC13b010kS180nm
Vendor
Fraunhofer Institute Integrated Circuits and Systems (IIS)
Type
Silicon IP

Analog

Resolution bits
13 Bit

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

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Frequently asked questions about ADC IP cores

What is Ultra-Low-Power 6-13 Bit 1-10 kS/s 1.9 µW SAR ADC on XFAB XT018?

Ultra-Low-Power 6-13 Bit 1-10 kS/s 1.9 µW SAR ADC on XFAB XT018 is a ADC IP core from Fraunhofer Institute Integrated Circuits and Systems (IIS) listed on Semi IP Hub. It is listed with support for x-fab Available on request.

How should engineers evaluate this ADC?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this ADC IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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