How Secure DDR Interfaces Protect DRAM from Memory Attacks
Brett Murdock, Dana Neustadter (Synopsys)
Vendor:
Zixin Microelectronics Technology Co. Ltd.
Category:
DDR
DDR PHY & DDR Controller IP
Fully compliant with the DFI 4.0
Overview
Fully compliant with the DFI 4.0
Key features
- DDR4/DDR3/DDR2 PHY IP fully compliant with the DFI 4.0 Specification.
- LPDDR5/LPDDR4/LPDDR3/LPDDR2 PHY IP fully compliant with the DFI 4.0 Specification.
- Support speeds up to 4266Mbps.
- IP is split into 2 hard macros.
- One for commands, control and address pins and another for 8-bit data bus.
- Can support custom number of address bits.
- Compensation controller and Pads are provided for automatic driver and receiver termination impedance calibration
- Features include slew rate control, Per-bit de-skew, gate training, read and write leveling.
- JTAG signals also provided for Mentor/Synopsys and LogicVision
- Built in Self Test with a Pseudo Random Pattern Generator
- Built with Scannable flops
- Can be used in wirebond, flip-chip and cup configurations
Specifications
Identity
Part Number
ZX_DDR_432
Vendor
Zixin Microelectronics Technology Co. Ltd.
Type
Silicon IP
Controller / PHY
Controller + PHY
Files
Note: some files may require an NDA depending on provider policy.
Provider
Learn more about DDR IP core
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Frequently asked questions about DDR Interface IP
What is DDR PHY & DDR Controller IP?
DDR PHY & DDR Controller IP is a DDR IP core from Zixin Microelectronics Technology Co. Ltd. listed on Semi IP Hub.
How should engineers evaluate this DDR?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.