How Secure DDR Interfaces Protect DRAM from Memory Attacks
Brett Murdock, Dana Neustadter (Synopsys)
Vendor:
VeriSyno Microelectronics Co., Ltd.
Category:
DDR
DDR4 PHY
The DDR4 multiPHY is a mixed-signal IP solution designed to provide LPDDR3/LPDDR2/DDR3/DDR3U/DDR3L/DDR4 SDRAM connectivity in a S…
Overview
The DDR4 multiPHY is a complete mixed-signal IP solution designed to provide LPDDR3/LPDDR2/DDR3/DDR3U/DDR3L/DDR4 SDRAM connectivity in a System-On-a-Chip (SOC) design targeted to a specific fabrication process. The DDR4 multiPHY supports a range of SDRAM speeds, from DDR3-400 through DDR4-2400. Targeted toward supporting, x8 and x16 SDRAM components, DDR4 multiPHY supports interfaces of varying widths, from a minimum of 8 bits wide, in 8-bit increments. Delivered to customers as hardened IP components —Address/Command (AC), Data (DAT), PLL, and SSTL I/O Library —implementations of the DDR4 multiPHY are compatible with JEDEC DDR SDRAMs, helping ensure customer success.
Key features
- ? DDR4, LPDDR3, LPDDR2, DDR3, DDR3L, and DDR3U operation
- ?1.2V DDR4 SDRAMs operating at data rates up to 2400Mbps
- ?1.2V LPDDR2 SDRAMs operating at data rates up to 1066Mbps
- ?1.35V DDR3L SDRAMs operating at data rates up to 1866Mbps
- ?1.25V DDR3U SDRAMs operating at data rates up to 1600Mbps
- ? Scalable performance from 0 MBps LPDDR2/LPDDR3 through DDR4-2400
- ? Maximum controller clock frequency of 600 MHz resulting in maximum SDRAM data rate of 2400Mbps
- ? Data path width scales in 8-bit increments, with allowances for partially-populated upper-most byte enables any DRAM width
- ? Delivery of product as a hardened macrocell allows precise control of timing critical delay and skew paths
- ? Includes PLL and Digital Delay Lines necessary to meet timing specifications
- ? Multiple (4) memory rank support
What’s Included?
- We offer high-speed interface IPs designed for 28~90nm fabrication processes in various foundries. We can also customize porting IPs for customers requiring 90~180nm fabrications and support more advanced processes as needed.
Specifications
Identity
Part Number
DDR4 PHY
Vendor
VeriSyno Microelectronics Co., Ltd.
Type
Silicon IP
Controller / PHY
Controller + PHY
,
PHY
Standards & Interfaces
Memory
DDR4
Provider
HQ:
The People's Republic of China
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Frequently asked questions about DDR Interface IP
What is DDR4 PHY?
DDR4 PHY is a DDR IP core from VeriSyno Microelectronics Co., Ltd. listed on Semi IP Hub.
How should engineers evaluate this DDR?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.