Vendor: VeriSyno Microelectronics Co., Ltd. Category: DDR

DDR3/2 PHY

The DDR3/2 PHY is a mixed-signal IP solution designed to provide DDR 3/2 SDRAM connectivity in a System-On-a-Chip (SOC) design ta…

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Controller + PHY + 1 DDR3 View all specifications

Overview

The DDR3/2 PHY is a complete mixed-signal IP solution designed to provide DDR 3/2 SDRAM connectivity in a System-On-a-Chip (SOC) design targeted to a specific fabrication process. The DDR3/2 PHY supports a range of DDR3 SDRAM speeds, from DDR3-667 through DDR3-1600, with backward compatibility provided for DDR2-667 through DDR2-1066 devices. Targeted toward supporting x8 and x16 DDR3 SDRAM components, DDR3/2 PHY supports interfaces of varying widths, from a minimum of 8 bits wide, in 8-bit increments. Delivered to customers as hardened IP components— Address/Command, DATX8, and SSTL I/O Library—implementations of the DDR3/2 PHY are compatible with JEDEC DDR2 and DDR3 SDRAMs, helping ensure customer success.

Key features

  • ? DDR2/DDR3/DDR3U/DDR3L/LVCMOS operating modes
  • ? Compatible with JEDEC standard DDR2/DDR3/DDR3U/DDR3L SDRAMs
  • ? Scalable performance from DDR2-667 through DDR3-1600
  • ? Maximum controller clock frequency of 400MHz resulting in maximum SDRAM data rate of 1600 Mbps
  • ? Data path width scales in 8-bit increments
  • ? Delivery of product as hardened IP components allows precise control of timing critical delay and skew paths
  • ? Includes embedded PLL and DDLs necessary to meet timing specifications
  • ? Multiple memory-rank support, up to four ranks
  • ? DDR3 PHY-Controller interface runs at 1/4 the memory baud rate, simplifying core logic timing constraints
  • ? Write leveling delay line (WLDL) to compensate address and control versus data delays of up to 1 clock cycle or 2500ps
  • ? Write and read bit delay lines (BDLs) compensate per-bit delay skew of up to 600ps at fast PVT; delay resolution approximately 15ps under typical conditions
  • ? Locally calibrated master and slave delay lines minimize OCV and ACLV effects, and accommodate V, T timing drift; delay resolution approximately 15ps under typical conditions
  • ? At-speed loopback testing on both the address and data channels
  • ? Delay line oscillator test mode
  • ? MUX-scan ATPG

What’s Included?

  • We offer high-speed interface IPs designed for 28~90nm fabrication processes in various foundries. We can also customize porting IPs for customers requiring 90~180nm fabrications and support more advanced processes as needed.

Specifications

Identity

Part Number
DDR3/2 PHY
Vendor
VeriSyno Microelectronics Co., Ltd.
Type
Silicon IP
Controller / PHY
Controller + PHY , PHY

Standards & Interfaces

Memory
DDR3

Provider

VeriSyno Microelectronics Co., Ltd.
HQ: The People's Republic of China
Contact VeriSyno Microelectronics Co., Ltd.

Learn more about DDR IP core

Which DDR SDRAM Memory to Use and When

This whitepaper provides an overview of the JEDEC memory standards to help SoC designers select the right memory solution, including IP, that best fits their application requirements.

Frequently asked questions about DDR Interface IP

What is DDR3/2 PHY?

DDR3/2 PHY is a DDR IP core from VeriSyno Microelectronics Co., Ltd. listed on Semi IP Hub.

How should engineers evaluate this DDR?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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