Overview
Fast Cycle RAM (FCRAM) is a DRAM technology with a specialized memory core technology that achieves faster random access times and offers lower power consumption than traditional DRAMs. FCRAM is a trademark of Fujitsu Ltd., Japan. As faster applications emerge in the networking and communications markets, there is a need for higher performance memories to meet the architectural requirements of these emerging applications. FCRAM memory technology addresses the needs of some of these emerging applications. For applications that require DRAM densities with random cycle performance approaching SRAM speeds, FCRAM provides a cost effective solution.
Lattice's FCRAM I controller core provides a simple and flexible solution to interfacing different FCRAM I memories to user application logic. On the memory side, the FCRAM I controller core interfaces to FCRAM I data bus widths with (configurable) 8 or 16 bit DDR memory interfaces. On the user side the core provides a simple command interface that accepts read, write, and refresh commands. The core interfaces to 256 Mbit FCRAM I devices (speed grades -60/CAS latency 3 and 4 and -55/CAS latency 3).
Learn more about DDR IP core
In order to fully capitalize on the benefits of DDR3 memories, it is important to have an efficient and easy to use DDR3 memory interface controller. A video processing application provides a good example of the key requirements of a DDR3 memory system and the features needed from a DDR3 Interface in similar stream-oriented data processing systems.
The union of Microcontroller Unit (MCU) intellectual property (IP) cores with FPGAs provides a far more flexible hardware platform than traditional MCU ASSPs.
Brett Murdock, Dana Neustadter (Synopsys)
In recent years, emerging industries such as AI, Internet of Things, 5G, and intelligent networked vehicles have flourished, and the high requirements for performance have greatly increased the scale and complexity of chips, constantly challenging IP limitations.
Dana Neustadter, Senior Product Manager for Security Solutions, and Brett Murdock, Director, Product Line Management for Memory Interface IP, Synopsys Solutions Group
DDR is most critical IP to SoC’s successful operation, because processors in SoC typically spends the majority of its cycles on reading and writing to DDR memory.
