Verification IP for Soundwire

A comprehensive VIP solution portfolio for Soundwire 1.0 used by SoC and IP designers to ensure comprehensive verification and protocol and timing compliance. Soundwire-Xactor implements a complete set of models, protocol checkers and compliance test suites in 100% native SystemVerilog and UVM.

Specifications

• Complete set of models for Soundwire master, monitor and device verification
• Master model can configure multiple data ports, frame shapes dynamically and generate payload streams to verify master and slave designs in complex system topologies
• System-level operations supported including allocating master and slave devices class objects (BFMs) to slave device map table and determines frame size and shape, sample interval and stream synchronization point including randomly configuration
• Automated payload streams generation per port based on stream class parameters such as data lanes used by each data payload stream, source/sinks of each data payload stream, number of channels, sample size and rate, and frame positioning parameters
• Multiple isochronous and asynchronous audio payload streams including PDM, PCM and random data

• Inject errors at all layers through callbacks
• Comprehensive assertions track Soundwire compliance coverage
• Functional coverage tracks range commands, payload transport modes, frame shapes, payload transport status
• Bus Protocol Analyzer depicts frame commands, payload/channel streams for each device, and frame and sub-frame map
• Comprehensive directed and constrained random compliance testsuite for Soundwire slave device achieves high protocol coverage
• Functional coverage tracks range of packet traffic, FSMs and complex operational sequences
• Tracker log monitors all levels and improves debug

• Soundwire BFM
• Compliance test suite
• User guide