Vendor: Arasan Chip Systems Inc. Category: I2C / I3C

I3C 1.1 Host Controller

The MIPI I3C host interface is an evolutionary standard that improves upon the features of I2C, while maintaining backward compat…

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Overview

The MIPI I3C host interface is an evolutionary standard that improves upon the features of I2C, while maintaining backward compatibility. This standard offers a flexible multi-drop interface between the host processor and peripheral sensors to support the growing usage of sensors in embedded systems.

The I3C Host Controller IP implements Host Controller functionality as defined by the MIPI Alliance’s I3C Specification. The I3C bus is used for various sensors in the mobile/automotive system where the Host Controller transfers data and control between itself and various sensor devices. The I3C Host Controller implements support for legacy I2C Device Controllers, Clock frequency scaling, Open-drain and Push-pull operation of I3C Interface, and Dynamic Addressing support.

Arasan has participated in multiple MIPI I3C Interop Workshops to ensure compliance of its I3C Host IP, I3C Device IP, I3C Software and HDK

 

Key features

  • Compliant with MIPI I3C Specification v1.1.1
  • Compliant with MIPI I3C HCI Specification v1.1
  • Supports up to 12.5 MHz operation using Push-Pull
  • Supported features,
    • Open-Drain and Push-pull type transactions (as required)
    • Supports legacy I2C devices
    • Dynamic addressing while supporting Static addressing for Legacy I2C devices
    • Legacy I2C messaging
    • I2C-like Single Data Rate messaging (SDR)
    • High Data Rate messaging modes (HDR-DDR mode)
    • Reception of In-band Interrupt support from the I3C Device Controllers
    • Reception of Hot-Join from newly added I3C Device Controllers
    • Support for Target reset
    • Support for group addressing
    • AHB Target Interface for Configuring/Controlling the IP with Interrupt output
    • AHB Interface for Host Controller DMA access
    • Support for up-to Eight rings in DMA mode and configurable as per the application requirement
    • Support for JESD403-1 Sideband Interface
  • Configurable FIFO sizes for PIO, DMA, Command, Response, and IBI Queue. Common FIFOs are used for both PIO and DMA mo

Block Diagram

I3C 1.1 Host Controller block diagram

What’s Included?

  • RMM compliant synthesizable RTL design in Verilog
  • Easy-to-use test environment
  • Synthesis scripts
  • Technical documents
  • Validated with 3rd Party UVM-based Device Controller VIP and available as an additional option

Specifications

Identity

Part Number
I3C 1.1 Host Controller
Vendor
Arasan Chip Systems Inc.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact Arasan Chip Systems Inc.

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Frequently asked questions about I2C / I3C IP cores

What is I3C 1.1 Host Controller?

I3C 1.1 Host Controller is a I2C / I3C IP core from Arasan Chip Systems Inc. listed on Semi IP Hub.

How should engineers evaluate this I2C / I3C?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this I2C / I3C IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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