M31 provides customers with a unique USB 1.1 PHY IP for IoT applications.
- USB 1.1
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
M31 provides customers with a unique USB 1.1 PHY IP for IoT applications.
USB2.0 Dual-Role PHY, HLMC 40LP
M31 provides customers the next generation of USB 2.0 IP with an extremely compact die area and lower active and suspend power co…
USB2.0 Dual-Role PHY, Samsung LFR6LP
M31 provides customers the next generation of USB 2.0 IP with an extremely compact die area and lower active and suspend power co…
USB2.0 Dual-Role PHY, Samsung LF6S
M31 provides customers the next generation of USB 2.0 IP with an extremely compact die area and lower active and suspend power co…
USB2.0 Dual-Role PHY, Samsung LF6
M31 provides customers the next generation of USB 2.0 IP with an extremely compact die area and lower active and suspend power co…
Gen7 supports 128Gbps and backward compatible with previous versions of PCIE.
An interconnect component connects initiators and targets in a system.
The bus converter module transforms 64-bit wide initiator data buses to smaller 32-bit target data buses or vice-versa.
Various bus types of protocols are available and employed in many applications, all of which require a bridge to operate safely a…
Decoder logic controls numerous targets based on input from the initiator.
The pervasive nature of Ethernet has made it an integral part of our connected world, driving communication speeds up to 1.6T.
10BASE-Te/100BASE-TX/100BASE-FX/1000BASE-T Energy Efficient Ethernet PHY; UMC 28nm HPC+ process
10BASE-Te/100BASE-TX/100BASE-FX/1000BASE-T Energy Efficient Ethernet PHY; UMC 28nm HPC+ process
The UCIe PHY & D2D Adapter IP portfolio includes 32Gbps UCIe- (UCIe-A) & Standard (UCIe-S) cores as per the latest UCIe v1.1 spec…
MIPI D-PHY
Coherent Network-on-Chip (NOC)
Scalable and area efficient interconnect solution optimized for memory coherent systems
Support for multiple protocol PCIE/CXL/Streaming
Retimer that are Physical Layer protocol aware and that interoperate with any pair of Components with any compliant channel on ea…
Retimer that are Physical Layer protocol aware and that interoperate with any pair of Components with any compliant channel on ea…
CXL is high bandwidth, low latency interconnect lies between host processor and memory devices/accelerators or other network inte…
CXL is high bandwidth, low latency interconnect lies between host processor and memory devices/accelerators or other network inte…