The MIPI® D-PHY TX+ is a proprietary implementation of the MIPI Camera Serial Interface 2 (CSI-2) and Display Serial Interface (D…
- MIPI PHY
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
The MIPI® D-PHY TX+ is a proprietary implementation of the MIPI Camera Serial Interface 2 (CSI-2) and Display Serial Interface (D…
MIPI D-PHY/LVDS Combo Receiver IP
The MXL-LVDS-MIPI-RX is a high-frequency, low-power, low-cost, source-synchronous, Physical Layer that supports the MIPI® Allianc…
The I²C master core is a simple I²C master that provides a link between the I²C bus and the AMBA APB.
Serial Lite IV Intel® FPGA IP Core
The Serial Lite IV Intel® FPGA Intellectual Property (IP) core is suitable for high-bandwidth data communication for chip-to-chip…
R-Tile is a FPGA companion tile that supports configurations up to PCIe 5.0 x16 in Endpoint (EP), Root Port (RP), and Transaction…
P-Tile is an FPGA companion tile available on Stratix® 10 DX and Agilex™ 7 FPGA F-Series device that natively supports PCIe* conf…
Stratix® 10 FPGAs incorporate the L/H-Tile chiplets which include a configurable, hardened protocol stack for PCIe that is compli…
PCI Express (PCIe*) protocol is a high-performance, scalable, and feature-rich serial protocol with data transfer rates from 2.5 …
The HDMI Intel FPGA intellectual property (IP) core provides support for the next generation of video display interface technolog…
Ethernet is ubiquitous across many markets and applications.
Intel® FPGA IP for Ethernet Products Portfolio
Triple Speed Ethernet Triple-Speed Ethernet Intel® FPGA intellectual property (IP) supports the 10 Mbps, 100 Mbps, and 1 Gbps dat…
DisplayPort Intel® FPGA IP Core
Intel now offers a fully VESA-compliant DisplayPort Intel® FPGA IP core v1.4.
Verification IP for DisplayPort/eDP
The Verification IP (VIP) for DisplayPort provides a comprehensive set of protocol, methodology, verification and productivity fe…
Physical interface for CSI-2 and DSI providing 2.5Gbps per lane of bandwidth Arasan’s MIPI D-PHY Analog Transceiver IP Core is fu…
Physical interface for CSI-2 providing 5.7Gbps per lane of bandwidth The MIPI C-PHY V1.0 improves throughput over a bandwidth-lim…
High Speed Data Bus (HSDB) IP Core
PHY and Mac layer hardware implementation for HSDB.
HDCP 1.4/2.2/2.3 for DisplayPort
HDCP 1.4/2.2/2.3 for DisplayPort
An optimum deployment of DCI in a Chipletized system would implement full DCI interfaces on all Chiplets.
USB1.1 FS/LS PHY, GloabalFoudries 55EF
M31 provides customers with a unique USB 1.1 PHY IP for IoT applications.
M31 provides customers with a unique USB 1.1 PHY IP for IoT applications.