GLOBALFOUNDRIES 28nm SLP 1.8v/1.0v SUBLVDSTX
GLOBALFOUNDRIES 28nm SLP 1.8v/1.0v SUBLVDSTX
- GlobalFoundries
- 28nm
- SLP
- Pre-Silicon
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
GLOBALFOUNDRIES 28nm SLP 1.8v/1.0v SUBLVDSTX
GLOBALFOUNDRIES 28nm SLP 1.8v/1.0v SUBLVDSTX
GLOBALFOUNDRIES 22nm FDSOI USB3.0 PHY
IP
GLOBALFOUNDRIES 22nm FDSOI USB2.0 OTG PHY
IP
Various onboard diagnostics protocols are currently available to be used for assembly line connectivity to various nodes etc.
Ethernet Filters for Precision Time Protocol on Automotive Ethernet
Various systems used in a car like Driver Assist System (ADAS) and Time-Sensitive Network (TSN) typically require large bandwidth…
SLVS Interface Driver, Fmax 600MHz - XFAB 180nm
SLVS Interface Driver, Fmax 600MHz - XFAB 180nm
LVDS interface Driver, Fmax 600MHz - XFAB 180nm
LVDS interface Driver, Fmax 600MHz - XFAB 180nm
IP
450 Mbit/s - 2 Gbit/s Display Transmitter
IP
0.6G - 12.5G Universal SerDes
USB 2.0 On-The-Go PHY; UMC 28nm HLP Process
USB 2.0 On-The-Go PHY; UMC 28nm HLP Process
USB2.0 On-The-Go PHY; UMC 28nm HPC RVT Logic Process_x005F_x000D_ cost down from FZOTG266HJ0C_A
USB2.0 On-The-Go PHY; UMC 28nm HPC RVT Logic Process cost down from FZOTG266HJ0C_A
USB1.1 PHY Feature USB 1.1 On-The-Go PHY; UMC 55nm Logic e-Flash Process
USB1.1 PHY Feature USB 1.1 On-The-Go PHY; UMC 55nm Logic e-Flash Process
TypeC CC channel for USBPD ; UMC 40NM LP Low-K process.
TypeC CC channel for USBPD ; UMC 40NM LP Low-K process.
Analog part of TX+RX lane operating at 1.25G~8Gbps , UMC 28nm HPC Process
Analog part of TX+RX lane operating at 1.25G~8Gbps , UMC 28nm HPC Process
28nm HPC x4 lane 10 Gbps SERDES
28nm HPC x4 lane 10 Gbps SERDES
MIPI Transmitter 80~1500MHz combo with CMOS input using MIFS C40LP Logic Process
MIPI Transmitter 80~1500MHz combo with CMOS input using MIFS C40LP Logic Process
MIPI RX 80Mbps~2.5Gbps ; UMC 28nm HPC+ process
MIPI RX 80Mbps~2.5Gbps ; UMC 28nm HPC+ process
Input 80MHz-440MHz, DQS delay 1/32 and 1/16 of FREF period, UMC 40nm LP/RVT Low-K logic process.
Input 80MHz-440MHz, DQS delay 1/32 and 1/16 of FREF period, UMC 40nm LP/RVT Low-K logic process.
CMM lane operating from 1.25G~8G ,UMC 28nm HPC Process
CMM lane operating from 1.25G~8G ,UMC 28nm HPC Process