What is I²C Master?
I²C Master is a I2C / I3C IP core from Frontgrade Gaisler listed on Semi IP Hub.
Vendor:
Frontgrade Gaisler
Category:
I2C / I3C
I²C Master
The I²C master core is a simple I²C master that provides a link between the I²C bus and the AMBA APB.
Overview
The I²C master core is a simple I²C master that provides a link between the I²C bus and the AMBA APB.
The I²C-master core is a modified version of the OpenCores I²C-Master where the WISHBONE interface has been replaced with an AMBA APB interface. The core is compatible with Philips I²C standard and supports 7- and 10-bit addressing. Standard-mode (100 kb/s) and Fast-mode (400 kb/s) operation are supported directly.
Key features
- AMBA APB interface
- Supports 7- and 10-bit addressing
- Bus arbitration (multi master operation)
- Software programmable clock frequency
- Clock stretching
Block Diagram
I²C to AHB Bridge block diagram
Specifications
Identity
Part Number
I²C to AHB Bridge
Vendor
Frontgrade Gaisler
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
Sweden
Frequently asked questions about I2C / I3C IP cores
How should engineers evaluate this I2C / I3C?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this I2C / I3C IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.