Vendor: Altera Category: PCI Express

P-Tile PCIe* Hard IP

P-Tile is an FPGA companion tile available on Stratix® 10 DX and Agilex™ 7 FPGA F-Series device that natively supports PCIe* conf…

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Overview

P-Tile is an FPGA companion tile available on Stratix® 10 DX and Agilex™ 7 FPGA F-Series device that natively supports PCIe* configurations up to 4.0 x16 in Endpoint (EP), Root Port (RP), and Transaction Layer (TL) Bypass Modes.

Standards & Specifications Compliance

  • PCIe Base Specification Revision 4.0
  • Single Root I/O Virtualization and Sharing Specification Rev. 1.1
  • PHY Interface for PCIe Architectures, Version 4.0
  • Virtual I/O Device (VIRTIO) Version 1.0
  • P-Tile PCIe Hard IP successfully passed PCI-SIG Compliance testing. Results posted on PCI-SIG Integrators list.

Features

  • Complete protocol stack including the transaction, data link, and physical layers implemented as Hard IP
  • PIPE mode support
  • Natively supports PCIe* 4.0/3.0 configurations with support for 2.0/1.0 configurations support via link down-training
  • Port Bifurcation capabilities: four x4 root ports, two x8 endpoints
  • Support TL-Bypass mode in both upstream and downstream modes
  • Up to 512B Maximum Payload Size (MPS)
  • Up to 4096-byte (4 KB) Maximum Read Request Size (MRRS)
  • Separate reference clock with independent spread spectrum Clocking (SRIS)
  • Separate reference clock with no spread spectrum clocking (SRNS)
  • Common reference clock architecture
  • Independent PERST to handle two reset operations (x8x8 EP and x8x8 TL Bypass)
  • Advanced Error Reporting (PF only)
  • Support for D0 and D3 PCIe power states
  • Lane margining at receiver
  • Retimers presence detection
  • Supports autonomous Hard IP mode that allows the PCIe Hard IP to communicate with the Host before the FPGA configuration and entry into user mode are complete
  • FPGA core Configuration via PCIe link (CVP Init and CVP Update) and Partial Reconfiguration (PR) over PCIe link

Multifunction and Virtualization Features

  • SR-IOV support (8 PFs, 2K VFs per each Endpoint)
  • VirtIO support via configuration intercept interface
  • Scalable I/O and Shared Virtual Memory (SVM) support
  • Access Control Service (ACS)
  • Alternative Routing-ID Interpretation (ARI)
  • Function Level Reset (FLR)
  • Suppot for TLP Processing Hint (TPH)
  • Address Translation Services (ATS)
  • Process Address Space ID (PasID)

User Interface Features

  • Avalon® Streaming Interface (Avalon-ST)
  • User packet interface with separate header, data, and prefix
  • Dual segmented user packet interface with the ability to handle up to two TLPs in any given cycle (x16 core only)
  • Extended Tag Support
  • 10-bit Tag Support (maximum of 768 outstanding tags (x16) / 512 outstanding tags (x4/x8) at any given time, for all functions combined)

Complementary IPs

  • Scalable Switch IP for PCI Express
  • Multi Channel DMA IP for PCI Express (AVMM / AVST Interfaces)

Driver Support

  • Linux device drivers
  • Windows device drivers (Stratix 10 only) (Jungo: partner-enabled device drivers)

IP Debug Features

  • Debug toolkit features:
  • Protocol and link status information
  • Basic and advanced debugging capabilities including PMA register access and Eye Viewing capability

Block Diagram

P-Tile PCIe* Hard IP block diagram

Specifications

Identity

Part Number
P-Tile PCIe* Hard IP
Vendor
Altera
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Altera
HQ: USA
Contact Altera

Learn more about PCI Express IP core

Frequently asked questions about PCIe IP cores

What is P-Tile PCIe* Hard IP?

P-Tile PCIe* Hard IP is a PCI Express IP core from Altera listed on Semi IP Hub.

How should engineers evaluate this PCI Express?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PCI Express IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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