Vendor: Mixel, Inc. Category: Multi-Protocol PHY

MIPI D-PHY/LVDS Combo Receiver IP

The MXL-LVDS-MIPI-RX is a high-frequency, low-power, low-cost, source-synchronous, Physical Layer that supports the MIPI® Allianc…

Overview

The MXL-LVDS-MIPI-RX is a high-frequency, low-power, low-cost, source-synchronous, Physical Layer that supports the MIPI® Alliance Standard for D-PHY and compatible with the TIA/EIA-644 LVDS standard.

The IP is configured as a MIPI slave and consists of 5 lanes: 1 Clock lane and 4 data lanes, which make it suitable for display serial interface applications (DSI).

The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed Data traffic while low power functions are mostly used for control.

Key features

  • Consists of 1 Clock lane and 4 Data lanes
  • Up to 4.0 Gbps data throughput
  • Supports the MIPI Standard 1.0 for D-PHY
  • Compatible with TIA/EIA-644 LVDS standard
  • Supports both high speed and low-power modes
  • 80 Mbps to 1 Gbps data rate in MIPI high speed mode
  • 140 Mbps to 945 Mbps data rate in LVDS high speed mode
  • 10 Mbps data rate in low-power mode
  • High Speed De-Serializers included
  • Low power CMOS design
  • Power down mode
  • 1.2V/3.3V dual power supply

Block Diagram

MXL-LVDS-DPHY-DSI-TX block diagram

Specifications

Identity

Part Number
MXL-LVDS-DPHY-DSI-TX
Vendor
Mixel, Inc.

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Mixel, Inc.
HQ: USA

Learn more about Multi-Protocol PHY IP core

MIPI deployment in ultra-low-power streaming sensors

This article focuses on low-power scenarios with streaming sensors connected to a processor via MIPI. After a short overview of low-duty cycle sensor principles, we explore how a streaming image sensor leverages those principles, show how one semiconductor company uses MIPI CSI-2® and D-PHY interfaces in their imaging solution, and touch on use cases for ultra-low-power streaming sensors deploying MIPI.

Frequently asked questions about Multi-Protocol PHY IP cores

What is MIPI D-PHY/LVDS Combo Receiver IP?

MIPI D-PHY/LVDS Combo Receiver IP is a Multi-Protocol PHY IP core from Mixel, Inc. listed on Semi IP Hub.

How should engineers evaluate this Multi-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Multi-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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