Stratix® 10 FPGAs incorporate the L/H-Tile chiplets which include a configurable, hardened protocol stack for PCIe that is compliant with PCIe Base Specification 3.0. This Avalon® Streaming Interface Hard IP supports PCIe 1.0, 2.0, and 3.0 data rates and x1, x2, x4, x8, or x16 configurations, including support for SR-IOV functionality.
Standards & Specifications Compliance
- L/H Tile PCIe Hard IP has passed PCI-SIG Compliance testing. Refer to PCI-SIG Integrators List.
Features
- Complete protocol stack including the Transaction, Data Link, and Physical Layers implemented as hard IP.
- x1, x2, x4, x8, and x16 configurations with x1.0, 2.0, or 3.0 lane rates for Native Endpoints and Root Ports.
- Avalon® streaming interface 256-bit interface to the Application Layer except for 3.0 x16 variants.
- Avalon® streaming interface 512-bit interface at 250 MHz to the Application Layer for 3.0 x16 variants.
- Instantiation as a stand-alone IP core from the Intel® Quartus® Prime Pro Edition IP Catalog or as part of a system design in Platform Designer.
- Dynamic design example generation.
- Configuration via Protocol (CvP) providing separate images for configuration of the periphery and core logic.
- PHY interface for PCIe (PIPE) or serial interface simulation using IEEE encrypted models.
- Testbench bus functional model (BFM) supporting x1, x2, x4, and x8 configurations.
- Support for a 3.0x16 BFM simulation model using Avery testbench. Refer to AN-811: Using the Avery BFM for PCIe 3.0 x16 Simulation on Intel® Stratix® 10 Devices.
- Native PHY Debug Master Endpoint (NPDME). For more information, refer to Intel® Stratix® 10 L-and H-Tile Transceiver PHY User Guide.
- Autonomous Hard IP mode, allowing the PCIe IP core to begin operation before the FPGA fabric is programmed. This mode is enabled by default. It cannot be disabled.
- Dedicated 69.5 kilobyte (KB) receive buffer.
- End-to-end cyclic redundancy check (ECRC).
- Base address register (BAR) checking logic.
- Support for Separate Reference Clock With No Spread Spectrum architecture (SRNS), but not for Separate Reference Clock With Independent.
- Spread Spectrum architecture (SRIS).
Single Root I/O Virtualization (SR-IOV) Feature Support (Only H-Tile)
- Separate Configuration Spaces for up to four PCIe Physical Functions (PFs) and a maximum of 2048 Virtual Functions (VFs).
- Advanced Error Reporting (AER) for PFs.
- Address Translation Services (ATS) and TLP Processing Hints (TPH) capabilities.
- Control Shadow Interface to read the current settings for some of the VF Control Register fields in the PCI and PCIe Configuration Spaces.
- Function Level Reset (FLR) for PFs and VFs.
- Message Signaled Interrupts (MSI) for PFs.
- MSI-X for PFs and VFs.
Complementary IPs (Only H-tile)
- Avalon® Memory-Mapped (AVMM) Bridge and Multichannel DMA IP
Driver Support
- Linux device drivers
- Windows device drivers (Jungo: partner-enabled device drivers)
Debug Features Include an PCIe Link Inspector Tool Including the Following Features
- Read and write access to the Configuration Space registers.
- LTSSM monitoring.
- Read and write access to PCS and PMA registers.
