Verification IP for Universal Chiplet Interconnect Express (UCIe) up to 3.0
Specifications: UCIe v1.0, v1.1, v2.0, v3.0 Interfaces: FDI/RDI/PHY link DUT Types/Topology D2D Adapter, Phy, Protocol, Full Stac…
- Verification IP
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
Verification IP for Universal Chiplet Interconnect Express (UCIe) up to 3.0
Specifications: UCIe v1.0, v1.1, v2.0, v3.0 Interfaces: FDI/RDI/PHY link DUT Types/Topology D2D Adapter, Phy, Protocol, Full Stac…
Verification IP for eUSB 2 v2 and USB 2.0
Specifications: eusb2v2 rev0.9, USB 2.0 Interfaces: UTMI/ULPI/Serial/HSIC/EUSB2 (V1 & V2) DUT Types/Topology USB 2.0 - Host, Dev…
16-bit xSPI + PSRAM IP Solution including support for AP Memory's Xccela™ PSRAM and the latest LVpSRAM™
Arasan Chip Systems, the provider of IP for Mobile and Automobile SOC’s, presents its latest eUSB2 IP.
Arasan Chip Systems, the provider of IP for Mobile and Automobile SOC’s, presents its latest eUSB2 V2.0 IP.
InfiniNoC is a highly customizable interconnect fabric designed to provide a scalable, high-performance communication backbone for next-generation SoCs.
20G MSS (Multi-standard SerDes) PHY
20G MSS (Multi-standard SerDes) PHY
ONFI NAND PHY
MIPI RX PHY is a mass production IP for D-PHY v1.2 and C-PHY v1.2 protocols.
MIPI RX controller on SMIC 28nm
MIPI RX controller is a mass production IP in SMIC 28nm supported MIPI DSI & DCS protocols.
DSC decoder IP is compliant with standard VESA Display Stream Compression version 1.1/1.2/1.2a.
The Nuclei Bus Fabric is a Nuclei designed bus interconnect optimized especially for high-performance bus interconnections.
Ethernet Switch TSN 20x1G + 4x5G
Ethernet Switch TSN 20x1G + 4x5G
GF 0.13um BCD LIN PHY IP, >20Kbps - GlobalFoundries 130nm
GF 0.13um BCD LIN PHY IP, >20Kbps - GlobalFoundries 130nm
GF 0.13um BCD CAN-FD PHY IP, > 5Mbps - GlobalFoundries 130nm
GF 0.13um BCD CAN-FD PHY IP, > 5Mbps - GlobalFoundries 130nm
USB 1.1 Device The USB 1.1 Device IP Core is an USB 1.1 compliant device core with optional AHB, APB, PCI, or Custom bus interfac…
The xSPI/PSRAM master IP is easy to use, simple to work with, quick to operate, and reliable under all conditions.
Serial RapidIO is a communication protocol developed to ensure fast and reliable interconnection between the vendor's boards.
Ethernet IP Core compliant with 100BASE-TX and 1000BASE-T
The Ethernet IP Core is compliant with 100BASE-TX and 1000BASE-T, supporting all commonly used PHY interfaces like MII, GMII, RGM…
The SpaceFibre IP core supports up to 8 lanes.