Vendor: Xilinx, Inc. Category: Protocol Bridge

AXI Slave Burst

The LogiCORE® IP AXI Slave Burst is an interface between the AXI4 memory-mapped interface to the IPIC (IP Inter Connect).

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Overview

The LogiCORE® IP AXI Slave Burst is an interface between the AXI4 memory-mapped interface to the IPIC (IP Inter Connect). This core is designed to provide a smooth migration path to the burst-supported IP from PLBv46 to AXI4 with minor updates in the interface. The core provides a point to point bi-directional interface between a user IP core and the AXI4 interconnect. This core acts as master on IPIC while it behaves as a slave on AXI4.

Key features

  • AXI4 Interface: 32 Bit Address bus, 32/64/128 Bit configurable data bus
  • IPIC Interface: 32 Bit Address bus, 32/64/128 Bit configurable data bus
  • Supports 1:1 (AXI4:IPIC) synchronous clock
  • Supports 1:1 (AXI4:IPIC) data width
  • AXI4 Interface
  • IPIC Interface

Specifications

Identity

Part Number
AXI Slave Burst
Vendor
Xilinx, Inc.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Xilinx, Inc.
HQ: USA
Contact Xilinx, Inc.

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Frequently asked questions about Protocol Bridge IP cores

What is AXI Slave Burst?

AXI Slave Burst is a Protocol Bridge IP core from Xilinx, Inc. listed on Semi IP Hub.

How should engineers evaluate this Protocol Bridge?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Protocol Bridge IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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