Overview
PSI1250MP is a multi-protocol SERDES capable of operating at up to 12.5Gbps. PSI1250MP can provide interfaces for many applications operating from 9.5Gbps to 12.5Gbps. It also provides interfaces for applications with 1/2, 1/4 and 1/8 speed. Fig. 1 shows the simplified top-level block diagram of this module. At the RX side the serial input data goes through the input stage with linear equalization. The Clock and data recovery (CDR) circuit receives the data. It then extracts the clock, and provides the clock and the retimed data to the de-serializer. The de-serializer converts the serial data to 8, 10, 16, 20, 32 or 40 bit parallel data with corresponding rx-clk. A DFE (Decision Feedback Equalization) block has been implemented in this module, and for the cases where a higher jitter tolerance is required, it is enabled. A Loss Of Signal (LOS) detector detects if there are valid data at the input. At the TX side the serialized data goes through the output driver. Depending on the application, transmitter can serialize 8, 10, 16, 20, 32 or 40 bit parallel data to a differential serial output. To further improve the jitter performance there are programmable pre-emphasis capabilities at the transmitter output stage. In addition near end serial and far end parallel loopback are implemented to be able to test the module. To improve signal integrity the block also includes a calibration circuit providing control signals to make the transmitter output resistance and the receiver input resistance within 50Ω±5%.
Learn more about Multi-Protocol PHY IP core
Morgan State University (MSU) recently received an Apple Innovation Grant, designed to support engineering schools as they develop their silicon and hardware technologies. The New Silicon Initiative (NSI) is designed to inspire and prepare students for careers in hardware engineering, computer architecture, and silicon chip design.
Increasingly, more of the focus on mobile has centered around cloud datacenters and the networking to get the data back and forth between these datacenters and the mobile device. Functions like voice recognition and mapping depend on the ability to split the functionality between the smartphone, for local processing like encryption and compression, and the back end, where a large number of servers can do the heavier lifting before returning the results.
Steven Brown
The Cadence 10G multi-protocol PHY was architected to address this exact challenge. Designed to scale across multiple process nodes, it consolidates PCI Express (PCIe), USB, DisplayPort, Ethernet, and other interfaces into a single, compact, silicon-efficient block. What sets it apart is simultaneous multi-protocol support, which enables multiple data paths without duplicating hardware, requiring extra board connectors, or paying the area and power penalty of separate IP blocks.
