Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
1G IP/UDP full HW Stack Transmitter / Receiver
To efficient transfer large amount of data and off-load the system processor, BitSim has launched its IP, Bit-UDP Ethernet.
OT3910bj is a set of cells designed for implementing the transmitter, receiver and associated bias function for LVDS point to poi…
The TRC5024CPA is a four lane Gen 1 and 2 PCI Express Physical layer (Phy) Phy IP core, delivering high-speed serial data transmi…
I3C Controller IP – Master / Slave, Parameterized FIFO, APB Bus
The DB-I3C-MS-APB Controller IP Core interfaces a microprocessor via the AMBA APB Bus to an I3C Bus, compliant to the MIPI I3C – …
IEEE 802.3cg® 10BASE-T1S Digital Controller
The CT25205 Digital IP core provides the PMA, PCS, and PLCA Reconciliation Sublayer building blocks of a standard IEEE 802.3cg® 1…
USB BCK Technology in TSMC (22nm, 40nm, 55nm, 65nm, 110nm)
In USB product series, M31 not only provides customers with a standard USB PHY solution, but also offers a unique BCK(Built-in Cl…
USB 1.1 PHY in TSMC(40nm, 55nm, 90nm ULP process )
M31 provides customers with a unique USB 1.1 PHY IP for IoT applications.
AHB Quad SPI Controller with Execute in Place (XIP)
The Quad Serial Peripheral Interface module either controls a serial data link as a master component, or reacts to a serial data …
The SPI to AHB Lite Bridge IP core is commonly used as a monitor interface to allow external devices to access the internal AHB b…
APB Channel with Decoder and Data Mux
The APB Channel provides the necessary infrastructure to connect as many as 16 AHB Slaves (numbered 0-15) to an APB Bus Master.
AHB Channel with Decoder and Data Mux IP Core
The AHB Channel provides the necessary infrastructure to connect as many as 7 AHB Slaves (numbered 1-7) to an AHB bus Master.
The AHB Fabric provides the necessary infrastructure to connect up to 16 shared AHB Slaves to up to 16 AHB-Lite Bus Masters.
The AXI to APB Bridge translates an AXI bus transaction (read or write) to an APB bus transaction.
The AHB Lite to AXI Bridge translates an AHB Lite bus transaction (read or write) to an AXI bus transaction.
The AXI Interconnect provides the necessary infrastructure to connect as many as 8 shared AXI Slaves to as many as 4 AXI Bus Mast…
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USB2.0 PHY - SMIC 110nm generic
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