What is PCIe 3.0 Transceiver?
PCIe 3.0 Transceiver is a Single-Protocol PHY IP core from Nano Silicon listed on Semi IP Hub. It is listed with support for smic.
Vendor:
Nano Silicon
Category:
Single-Protocol PHY
PCIe 3.0 Transceiver
Key features
- Standard PHY interface (PIPE) enables multiple IP sources for PCIe 3.0 MAC Layer
- Dual port PIPE with shared REF CLK configurable to be 2-lane PCIe PHY
- Supports 2.5 GT/s and 5.0 GT/s serial data transmission rate
- Supports 16- or 32-bit parallel interface when encoding/ decoding enabled
- Supports 20-bit parallel interface when encoding/ decoding bypassed
- Supports PCLK as PHY output
- Data and clock recovery from serial stream
- 8b/10b encoder/decoder and error indication
- Supports direct disparity control for use in transmitting compliance pattern
- Supports power change and rate change in same PCLK cycle
- Receiver detection
- Beacon transmission and reception
- Supports transmitting LFPS when power state changes
- Selectable TX margining
- Selectable TX de-emphasis, and signal swing values
- Compliant with PCIe 3.0 specification
Applications
- PC
- Data Storage
- Multimedia Devices
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| SMIC | 40nm | 40nm 400 nm | — |
Specifications
Identity
Part Number
PCIe3
Vendor
Nano Silicon
Type
Silicon IP
Standards & Interfaces
Supported Standards
PCIe Gen3
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
Australia
Frequently asked questions about Single-Protocol PHY IP
How should engineers evaluate this Single-Protocol PHY?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.