Vendor: Nano Silicon Category: Multi-Protocol PHY

PCIe/USB/SATA Combo PHY

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SMIC 40nm View all specifications

Key features

  • Standard PHY interface (PIPE) enables multiple IP sources for PCIe/USB/SATA MAC Layer
  • Dual port PIPE with shared REF_CLK configurable to be 2-lane PCIe PHY
  • Supports 2.5 GT/s and 5.0 GT/s serial data transmission rate in PCIe mode
  • Supports 5.0 GT/s serial data transmission rate in USB mode
  • Supports 1.5 GT/s, 3.0 GT/s and 6.0 GT/s serial data transmission rate in SATA mode
  • Supports 16- or 32-bit parallel interface when encoding/ decoding enabled
  • Supports 20-bit parallel interface when encoding/ decoding bypassed
  • Supports PCLK as PHY output
  • Data and clock recovery from serial stream
  • 8b/10b encoder/decoder and error indication
  • Supports direct disparity control for use in transmitting compliance pattern in PCIe mode
  • Supports power change and rate change in same PCLK cycle in PCIe/SATA mode
  • Receiver detection in PCIe/USB mode
  • Beacon transmission and reception in PCIe mode
  • Low Frequency Periodic Signaling (LFPS) transmission and reception in USB mode
  • COMWAKE, COMINIT and COMRESET (OOB) transmission and reception in SATA mode
  • Supports transmitting LFPS when power state changes
  • Selectable TX margining in PCIe/USB mode
  • Selectable TX de-emphasis, and signal swing values in PCIe mode
  • Compliant with PCIe/USB/SATA base specification

Applications

  • PC
  • Data Storage
  • Multimedia Devices

Silicon Options

Foundry Node Process Maturity
SMIC 40nm 40nm 400 nm —

Specifications

Identity

Part Number
USB_SATA_PCIe
Vendor
Nano Silicon
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Nano Silicon
HQ: Australia
Contact Nano Silicon

Learn more about Multi-Protocol PHY IP core

How a 16Gbps Multi-link, Multi-protocol SerDes PHY Can Transform Datacenter Connectivity

Increasingly, more of the focus on mobile has centered around cloud datacenters and the networking to get the data back and forth between these datacenters and the mobile device. Functions like voice recognition and mapping depend on the ability to split the functionality between the smartphone, for local processing like encryption and compression, and the back end, where a large number of servers can do the heavier lifting before returning the results.

One PHY, Zero Tradeoffs: Multi-Protocol PHY for Edge AI Interface Consolidation

The Cadence 10G multi-protocol PHY was architected to address this exact challenge. Designed to scale across multiple process nodes, it consolidates PCI Express (PCIe), USB, DisplayPort, Ethernet, and other interfaces into a single, compact, silicon-efficient block. What sets it apart is simultaneous multi-protocol support, which enables multiple data paths without duplicating hardware, requiring extra board connectors, or paying the area and power penalty of separate IP blocks.

Frequently asked questions about Multi-Protocol PHY IP cores

What is PCIe/USB/SATA Combo PHY?

PCIe/USB/SATA Combo PHY is a Multi-Protocol PHY IP core from Nano Silicon listed on Semi IP Hub. It is listed with support for smic.

How should engineers evaluate this Multi-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Multi-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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