Overview
Entry-level network-on-chip (NoC) IP for low power and cost efficiency.
Arteris FlexWay® 5 network-on-chip (NoC) IP is particularly well suited to cost-efficient, low-power IoT edge devices and microcontrollers (MCUs).
It revolutionizes SoC development with:
- Optimized interconnects
- Reduced time to market
- Improved performance
- Lower power consumption
- Compact die size
By automating design tasks and supporting tailored topologies, FlexWay enhances system responsiveness and includes features to help optimize battery life, system integrity and performance. FlexWay 5 is used around the world for secure, performant, and resilient designs in mobile, automotive, consumer, and enterprise applications.
Learn more about Network-On-Chip IP core
As software-defined vehicles reshape the automotive industry, collaborative innovation is becoming essential to developing secure, scalable computing platforms. Learn how Arteris is contributing to the European RIGOLETTO project, helping advance next-generation automotive architectures through expertise in Network-on-Chip technology, RISC-V integration, and high-performance semiconductor design.
When chip design and verification teams start a new project, they recognize the need for models that capture the design at a high level of abstraction. However, they tend to focus on acquiring or creating models of the IP blocks used to implement the device’s core functionality, while overlooking network-on-chip (NoC) interconnect IP until it’s too late.
SystemC TLM modeling helps AI chip architects analyze NoC data movement early, identify bandwidth and latency bottlenecks, optimize workload behavior, and reduce RTL-stage performance and integration risk. Learn more about how early NoC modeling improves AI system design and accelerates architectural decision-making in the article.
As AI designs continue to grow in complexity, managing massive data flows through fixed, point-to-point connections no longer scales efficiently. Designers are now dealing with hundreds of compute engines and memory instances, each with different performance requirements, all of which must move data simultaneously.
The design demands of today’s highly advanced system-on-chip (SoC) devices have long outgrown the capabilities of manual workflows to manage them effectively. As these chips become more complex, only sophisticated, high-performance, and scalable automation can ensure that every component of the SoC functions seamlessly.
On March 24, the 2026 XuanTie RISC-V Ecosystem Conference, hosted by Alibaba DAMO Academy, was held in Shanghai. Hundreds of industry and academic institutions from around the world—including Qualcomm, Arteris, Canonical, SHD Group, Haier, and ZTE—gathered to share cutting-edge practices in RISC-V.
