AHB Octal SPI Controller with PSRAM and XIP Support
The Octal SPI Memory Controller IP core is a serial peripheral interface (SPI) master which controls an external serial device, u…
- SPI / QSPI XSPI
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
AHB Octal SPI Controller with PSRAM and XIP Support
The Octal SPI Memory Controller IP core is a serial peripheral interface (SPI) master which controls an external serial device, u…
FlexCAN Controller for CAN 2.0 with CAN-FD
The FlexCAN controller is a configurable, synthesizable core implementing the CAN protocol (ISO 11898-1), CAN with Flexible Data …
Silicon agnostic Ethernet TSN MAC IP with speeds of 10G and 25G, based IEEE 802.3 Ethernet Layer 2 solution with support for key …
10G Ultra Low Latency Ethernet Solution
The 10Gbps Ultra Low Latency Ethernet IP solution offers a fully integrated IEEE802.3 compliant package for NIC (Network Interfac…
USB 3.0 OTG High / Full / Low- Speed Dual Role IP Core
USB 3.0 OTG Controller IP is based on the latest USB 3.0 specification from USB Implementer Forum (USBIF) and is compatible with…
Atomic Rules UDP Offload Engine (UOE) is a UDP FPGA IP Core that allows for immediate operation at 10, 25, 40, 50, 100 or 400 GbE.
AXI Quad SPI Controller with Execute in Place (XIP)
The Ultra High-Speed cache memory is an adaptable, independent, non-coherent cache Intellectual Property (IP) featuring an cache …
The AL_EMAC_CORE Ethernet MAC Core is hardware implementation of Ethernet protocol defined by IEEE 802.3-2005 Specification.
CSI2 RX; Camera Serial Interface, MIPI Compliant
The CSI2 Receiver IP Interfaces between Camera module which has the transmitter and the application processor.
iWave provides the user application for PCI-e target bridge to access the control & status registers of custom logic and data tra…
1G Deep Buffering Memory Ethernet Switch IP Core
switch supporting buffering of large amounts of data in external DDR RAM The 1G deep buffering memory Ethernet Switch is an Ether…
LTTS USB 2.0 OTG controller are designed for compliance with USB2.0 specification Revision 2.0 and all associated ECN’s and USB O…
FPD LVDS Display Interface, 1 Port / 2 Port LCD Panel
The DB-FPD-LVDS-TX LVDS Display Interface IP Core interfaces parallel 18-bit/24-bit RGB Pixel Data with display timing VSYNC, HSY…
SPI Slave Serial Interface Controller
The SPI_SLAVE IP Core is an SPI compliant slave interface controller.
The CODEC_8B10B IP Core is a scalable 8B/10B Encoder/Decoder pair suitable for a wide range of serial data transmission applicati…
UART Serial Interface Controller
The UART_CONT IP Core is a robust UART-compliant serial interface controller capable of receiving and transmitting bits serially.
SPI Master Serial Interface Controller
The SPI_MASTER IP Core is an SPI compliant serial interface controller capable of driving up to 16 different slave devices in ful…
I2C Slave Serial Interface Controller
The I2C_SLAVE IP Core is a Philips® I2C compliant slave interface controller.
I2C Master Serial Interface Controller
The I2C_MASTER IP Core is a Philips® I2C compliant serial interface controller capable of driving a standard two-wire bus in sing…
UDP/IP – 100 GbE Protocol Hardware Stack
The DB-UDP-IP-100GbE-AMBA is a UDP/IP Hardware Stack / UDP Off-load Engine (UOE) with low latency, high-performance targeting 100…